From patchwork Thu Feb 5 15:25:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 5785191 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 79B22BF6C3 for ; Thu, 5 Feb 2015 15:28:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 676A020270 for ; Thu, 5 Feb 2015 15:28:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D4242022D for ; Thu, 5 Feb 2015 15:28:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YJOKB-0004k5-JT; Thu, 05 Feb 2015 15:26:35 +0000 Received: from metis.ext.pengutronix.de ([2001:6f8:1178:4:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YJOJm-0004XT-52 for linux-arm-kernel@lists.infradead.org; Thu, 05 Feb 2015 15:26:12 +0000 Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1YJOJN-0001Fw-GW; Thu, 05 Feb 2015 16:25:45 +0100 Received: from sha by dude.hi.pengutronix.de with local (Exim 4.84) (envelope-from ) id 1YJOJI-0004YF-EZ; Thu, 05 Feb 2015 16:25:40 +0100 From: Sascha Hauer To: Olof Johansson , Arnd Bergmann Subject: [PATCH 1/8] soc: Add MediaTek infracfg controller support Date: Thu, 5 Feb 2015 16:25:31 +0100 Message-Id: <1423149938-14471-2-git-send-email-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1423149938-14471-1-git-send-email-s.hauer@pengutronix.de> References: <1423149938-14471-1-git-send-email-s.hauer@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150205_072610_507335_263D1B48 X-CRM114-Status: GOOD ( 21.76 ) X-Spam-Score: -0.0 (/) Cc: Samuel Ortiz , Sascha Hauer , =?UTF-8?q?YH=20Chen=20=28=E9=99=B3=E6=98=B1=E8=B1=AA=29?= , linux-kernel@vger.kernel.org, Henry Chen , Rob Herring , kernel@pengutronix.de, Matthias Brugger , =?UTF-8?q?Yingjoe=20Chen=20=28=E9=99=B3=E8=8B=B1=E6=B4=B2=29?= , Eddie Huang , Lee Jones , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds support for the MediaTek infracfg controller found on the MT8135/MT8173 SoCs. The infracfg controller contains miscellaneous registers for controlling peripheral resets and clocks. Signed-off-by: Sascha Hauer --- .../devicetree/bindings/soc/mediatek/infracfg.txt | 29 +++++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/mediatek/Kconfig | 12 ++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-infracfg.c | 127 +++++++++++++++++++++ 6 files changed, 171 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/infracfg.txt create mode 100644 drivers/soc/mediatek/Kconfig create mode 100644 drivers/soc/mediatek/Makefile create mode 100644 drivers/soc/mediatek/mtk-infracfg.c diff --git a/Documentation/devicetree/bindings/soc/mediatek/infracfg.txt b/Documentation/devicetree/bindings/soc/mediatek/infracfg.txt new file mode 100644 index 0000000..1912b83 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/infracfg.txt @@ -0,0 +1,29 @@ +MediaTek infracfg Controller +============================ + +The infracfg controller contains miscellaneous registers for controlling +clocks, resets and bus settings. + +Required properties: +- compatible: must be one of: + mediatek,mt8135-infracfg + mediatek,mt8173-infracfg +- reg: Address range for the infracfg controller +- #reset-cells: 1, see below + +Specifying reset lines connected to the infracfg controller +=========================================================== + +The infracfg controller provides various reset sources to other modules. +Device nodes using these reset sources should specify the reset lines in +a property containing a phandle to the infracfg node and a reset index. +See include/dt-bindings/reset-controller/-resets.h for a list of valid +indices. + +Example: + + infracfg: infracfg@10001000 { + #reset-cells = <1>; + compatible = "mediatek,mt8135-infracfg"; + reg = <0 0x10001000 0 0x1000>; + }; diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 76d6bd4..d8bde82f0 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -1,5 +1,6 @@ menu "SOC (System On Chip) specific Drivers" +source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/ti/Kconfig" source "drivers/soc/versatile/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 063113d..70042b2 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -2,6 +2,7 @@ # Makefile for the Linux Kernel SOC specific device drivers. # +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_SOC_TI) += ti/ diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig new file mode 100644 index 0000000..3ad39fe --- /dev/null +++ b/drivers/soc/mediatek/Kconfig @@ -0,0 +1,12 @@ +# +# MediaTek SoC drivers +# +config MTK_INFRACFG + tristate "MediaTek infracfg controller support" + depends on ARCH_MEDIATEK || COMPILE_TEST + select REGMAP + help + The MediaTek infracfg controller found on MT8135 and MT8173 SoCs + contains several miscellaneous registers for clock, reset and bus + settings. Say yes here if you want to run your kernel on one of these + SoCs. diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile new file mode 100644 index 0000000..dbeb627 --- /dev/null +++ b/drivers/soc/mediatek/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c new file mode 100644 index 0000000..3bbd39b --- /dev/null +++ b/drivers/soc/mediatek/mtk-infracfg.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +struct mtk_infracfg { + struct regmap *regmap; + struct reset_controller_dev rcdev; +}; + +static int mtk_infracfg_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mtk_infracfg *data = container_of(rcdev, struct mtk_infracfg, rcdev); + + return regmap_update_bits(data->regmap, 0x30 + ((id / 32) << 2), BIT(id % 32), ~0u); +} + +static int mtk_infracfg_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct mtk_infracfg *data = container_of(rcdev, struct mtk_infracfg, rcdev); + + return regmap_update_bits(data->regmap, 0x30 + ((id / 32) << 2), BIT(id % 32), 0); +} + +static int mtk_infracfg_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret = mtk_infracfg_reset_assert(rcdev, id); + if (ret) + return ret; + + return mtk_infracfg_reset_deassert(rcdev, id); +} + +static struct reset_control_ops mtk_infracfg_reset_ops = { + .assert = mtk_infracfg_reset_assert, + .deassert = mtk_infracfg_reset_deassert, + .reset = mtk_infracfg_reset, +}; + +static struct regmap_config mtk_infracfg_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int mtk_infracfg_probe(struct platform_device *pdev) +{ + struct mtk_infracfg *data; + struct resource *res; + void __iomem *base; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + data->regmap = devm_regmap_init_mmio(&pdev->dev, base, + &mtk_infracfg_regmap_config); + if (IS_ERR(data->regmap)) + return PTR_ERR(data->regmap); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = 64; + data->rcdev.ops = &mtk_infracfg_reset_ops; + data->rcdev.of_node = pdev->dev.of_node; + + return reset_controller_register(&data->rcdev); +} + +static int mtk_infracfg_remove(struct platform_device *pdev) +{ + struct mtk_infracfg *data = platform_get_drvdata(pdev); + + reset_controller_unregister(&data->rcdev); + + return 0; +} + +static const struct of_device_id mtk_infracfg_dt_ids[] = { + { + .compatible = "mediatek,mt8173-infracfg", + }, { + .compatible = "mediatek,mt8135-infracfg", + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, mtk_infracfg_dt_ids); + +static struct platform_driver mtk_infracfg_driver = { + .probe = mtk_infracfg_probe, + .remove = mtk_infracfg_remove, + .driver = { + .name = "mtk-infracfg", + .of_match_table = mtk_infracfg_dt_ids, + }, +}; + +module_platform_driver(mtk_infracfg_driver); + +MODULE_AUTHOR("Sascha Hauer "); +MODULE_DESCRIPTION("MediaTek infracfg controller"); +MODULE_LICENSE("GPL");