From patchwork Fri Feb 13 15:11:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 5825611 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id EA3D79F37F for ; Fri, 13 Feb 2015 15:17:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2EB3020263 for ; Fri, 13 Feb 2015 15:17:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5263320148 for ; Fri, 13 Feb 2015 15:17:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YMHx3-0004Gw-1v; Fri, 13 Feb 2015 15:14:41 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YMHv8-00036X-OK for linux-arm-kernel@lists.infradead.org; Fri, 13 Feb 2015 15:12:43 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id t1DFCOWt024208; Fri, 13 Feb 2015 09:12:24 -0600 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1DFCNQL019373; Fri, 13 Feb 2015 09:12:23 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Fri, 13 Feb 2015 09:12:23 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t1DFBvlZ030611; Fri, 13 Feb 2015 09:12:21 -0600 From: Tomi Valkeinen To: Tony Lindgren , Paul Walmsley , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , , Subject: [PATCH 9/9] RFC: ARM: DRA7: enable DSS_DESHDCP_CLKEN Date: Fri, 13 Feb 2015 17:11:26 +0200 Message-ID: <1423840286-18377-10-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.3.0 In-Reply-To: <1423840286-18377-1-git-send-email-tomi.valkeinen@ti.com> References: <1423840286-18377-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150213_071242_904935_D422C5FC X-CRM114-Status: UNSURE ( 9.68 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -5.0 (-----) Cc: Nishanth Menon , Tero Kristo , Tomi Valkeinen , Felipe Balbi X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DRA7xx's CTRL_CORE_CONTROL_IO_2 register contains bits for various subsystems, including PCIe, DCAN, QSPI and DSS. At the moment only DCAN bits are used by the SW via syscon. For DSS there is DSS_DESHDCP_CLKEN bit. This (presumably) enables a clock related to DSS's HDCP. If that clock is off, DSS module does not start at all, causing OCP errors. This means that the HWMOD code is not able to reset and initialize DSS. Signed-off-by: Tomi Valkeinen --- arch/arm/mach-omap2/io.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index a1bd6affb508..2206fb13f195 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -700,6 +700,17 @@ void __init dra7xx_init_early(void) dra7xx_hwmod_init(); omap_hwmod_init_postsetup(); omap_clk_soc_init = dra7xx_dt_clk_init; + + if (soc_is_dra7xx()) { + u32 v; + const u16 ctrl_core_control_io_2 = 0x558; + + /* set CTRL_CORE_CONTROL_IO_2:DSS_DESHDCP_CLKEN */ + + v = omap_ctrl_readl(ctrl_core_control_io_2); + v |= 1; + omap_ctrl_writel(v, ctrl_core_control_io_2); + } } void __init dra7xx_init_late(void)