From patchwork Fri Feb 20 18:01:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 5858131 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D6C7BBF440 for ; Fri, 20 Feb 2015 18:20:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A3950204FC for ; Fri, 20 Feb 2015 18:20:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65235204B5 for ; Fri, 20 Feb 2015 18:20:03 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YOs7k-0007RZ-8k; Fri, 20 Feb 2015 18:16:24 +0000 Received: from mail-we0-x243.google.com ([2a00:1450:400c:c03::243]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YOruQ-0002Of-CR for linux-arm-kernel@lists.infradead.org; Fri, 20 Feb 2015 18:02:41 +0000 Received: by wesk11 with SMTP id k11so2073022wes.1 for ; Fri, 20 Feb 2015 10:02:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:subject:date:message-id:in-reply-to:references; bh=gUDut2FGMhTuppswKlYLRN9EF7JWt5a8AEUfRPzA81Y=; b=gdCMvLInOAsocOMoLoRwzrlqaPxG8ghq+NiJNuG5gEtn4U65m5ncoGlwk5H/3wnZUm Ayn+z70p6F2F7rSZOSliLlP9A63YkDGyFgyEWCdcwYwOQbk0rKW4q09qBuUvOBeSqodG fvQoEOswIKLXr+g1jH5JvrS2YhCtWvpoT4Wg4+kxHVPuKDMrTU0NlNdPuAoTQCdwgYXH sXspYc0kpfTnaucb3C3O5D5lmcx31XIAxYKFYhw2ii54hN3ywU06MokWIv7eUv2jzQiP Ivd0+BMhY+pq//jpYxdUJ9AzJQueagkjB6FqldpJK1NWGtDnbvEaTLGDURigZzRErTmA TkdA== X-Received: by 10.194.110.233 with SMTP id id9mr21496479wjb.136.1424455336190; Fri, 20 Feb 2015 10:02:16 -0800 (PST) Received: from lmecul0520.st.com. (169.20.90.92.rev.sfr.net. [92.90.20.169]) by mx.google.com with ESMTPSA id hs7sm3398370wib.4.2015.02.20.10.02.13 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Feb 2015 10:02:15 -0800 (PST) From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Jonathan Corbet , Maxime Coquelin , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Daniel Lezcano , Thomas Gleixner , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Arnd Bergmann , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Joe Perches , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org Subject: [PATCH v2 16/18] ARM: dts: Introduce STM32F429 MCU Date: Fri, 20 Feb 2015 19:01:15 +0100 Message-Id: <1424455277-29983-17-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1424455277-29983-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1424455277-29983-1-git-send-email-mcoquelin.stm32@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150220_100238_761645_21E60B72 X-CRM114-Status: GOOD ( 12.96 ) X-Spam-Score: 3.0 (+++) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SBL_CSS, RP_MATCHES_RCVD, T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The STMicrolectornics's STM32F419 MCU has the following main features: - Cortex-M4 core running up to @180MHz - 2MB internal flash, 256KBytes internal RAM - FMC controller to connect SDRAM, NOR and NAND memories - SD/MMC/SDIO support - Ethernet controller - USB OTFG FS & HS controllers - I2C, SPI, CAN busses support - Several 16 & 32 bits general purpose timers - Serial Audio interface - LCD controller Signed-off-by: Maxime Coquelin --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32f429-disco.dts | 41 ++++ arch/arm/boot/dts/stm32f429.dtsi | 396 ++++++++++++++++++++++++++++++++++ 3 files changed, 438 insertions(+) create mode 100644 arch/arm/boot/dts/stm32f429-disco.dts create mode 100644 arch/arm/boot/dts/stm32f429.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 91bd5bd..d7da0ef 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -442,6 +442,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ stih416-b2000.dtb \ stih416-b2020.dtb \ stih416-b2020e.dtb +dtb-$(CONFIG_ARCH_STM32)+= stm32f429-disco.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts new file mode 100644 index 0000000..0e79cc1 --- /dev/null +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -0,0 +1,41 @@ +/dts-v1/; +#include "stm32f429.dtsi" + +/ { + model = "STMicroelectronics's STM32F429i-DISCO board"; + compatible = "st,stm32f429i-disco", "st,stm32f429"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/ram rdinit=/linuxrc"; + linux,stdout-path = &usart1; + }; + + memory { + reg = <0xd0000000 0x800000>; + }; + + aliases { + ttyS0 = &usart1; + }; + + soc { + usart1: usart@40011000 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + red { + #gpio-cells = <2>; + label = "Front Panel LED"; + gpios = <&gpiog 14 0>; + linux,default-trigger = "heartbeat"; + }; + green { + #gpio-cells = <2>; + gpios = <&gpiog 13 0>; + default-state = "off"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi new file mode 100644 index 0000000..5b3442a --- /dev/null +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -0,0 +1,396 @@ +/* + * Device tree for STM32F429 + */ +#include "armv7-m.dtsi" +#include +#include + +/ { + + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + clocks { + clk_sysclk: clk-sysclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <180000000>; + }; + + clk_hclk: clk-hclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <180000000>; + }; + + clk_pclk1: clk-pclk1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <45000000>; + }; + + clk_pclk2: clk-pclk2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <90000000>; + }; + + clk_pmtr1: clk-pmtr1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <90000000>; + }; + + clk_pmtr2: clk-pmtr2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <180000000>; + }; + + clk_systick: clk-systick { + compatible = "fixed-factor-clock"; + clocks = <&clk_hclk>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; + }; + + systick: timer@e000e010 { + clocks = <&clk_systick>; + + status = "okay"; + }; + + soc { + reset: reset@40023810 { + #reset-cells = <1>; + compatible = "st,stm32-reset"; + reg = <0x40023810 0x18>; + }; + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32-pinctrl"; + ranges = <0 0x40020000 0x3000>; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset GPIOA_RESET>; + st,bank-name = "GPIOA"; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x400 0x400>; + resets = <&reset GPIOB_RESET>; + st,bank-name = "GPIOB"; + }; + + gpioc: gpio@40020800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x800 0x400>; + resets = <&reset GPIOC_RESET>; + st,bank-name = "GPIOC"; + }; + + gpiod: gpio@40020c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0xc00 0x400>; + resets = <&reset GPIOD_RESET>; + st,bank-name = "GPIOD"; + }; + + gpioe: gpio@40021000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + resets = <&reset GPIOE_RESET>; + st,bank-name = "GPIOE"; + }; + + gpiof: gpio@40021400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1400 0x400>; + resets = <&reset GPIOF_RESET>; + st,bank-name = "GPIOF"; + }; + + gpiog: gpio@40021800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1800 0x400>; + resets = <&reset GPIOG_RESET>; + st,bank-name = "GPIOG"; + }; + + gpioh: gpio@40021c00 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1c00 0x400>; + resets = <&reset GPIOH_RESET>; + st,bank-name = "GPIOH"; + }; + + gpioi: gpio@40022000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + resets = <&reset GPIOI_RESET>; + st,bank-name = "GPIOI"; + }; + + gpioj: gpio@40022400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2400 0x400>; + resets = <&reset GPIOJ_RESET>; + st,bank-name = "GPIOJ"; + }; + + gpiok: gpio@40022800 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2800 0x400>; + resets = <&reset GPIOK_RESET>; + st,bank-name = "GPIOK"; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + st,pins { + tx = <&gpioa 9 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpioa 10 ALT7 NO_PULL>; + }; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + st,pins { + tx = <&gpioa 2 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpioa 3 ALT7 NO_PULL>; + }; + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + st,pins { + tx = <&gpiob 10 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpiob 11 ALT7 NO_PULL>; + }; + }; + }; + + usart4 { + pinctrl_usart4: usart4-0 { + st,pins { + tx = <&gpioa 0 ALT8 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpioa 1 ALT8 NO_PULL>; + }; + }; + }; + + usart5 { + pinctrl_usart5: usart5-0 { + st,pins { + tx = <&gpioc 12 ALT8 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpiod 2 ALT8 NO_PULL>; + }; + }; + }; + + usart6 { + pinctrl_usart6: usart6-0 { + st,pins { + tx = <&gpioc 6 ALT8 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpioc 7 ALT8 NO_PULL>; + }; + }; + }; + + usart7 { + pinctrl_usart7: usart7-0 { + st,pins { + tx = <&gpioe 8 ALT8 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpioe 7 ALT8 NO_PULL>; + }; + }; + }; + + usart8 { + pinctrl_usart8: usart8-0 { + st,pins { + tx = <&gpioe 1 ALT8 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpioe 0 ALT8 NO_PULL>; + }; + }; + }; + }; + + timer2: timer@40000000 { + compatible = "st,stm32-timer"; + reg = <0x40000000 0x400>; + interrupts = <28>; + resets = <&reset TIM2_RESET>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + timer3: timer@40000400 { + compatible = "st,stm32-timer"; + reg = <0x40000400 0x400>; + interrupts = <29>; + resets = <&reset TIM3_RESET>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + timer4: timer@40000800 { + compatible = "st,stm32-timer"; + reg = <0x40000800 0x400>; + interrupts = <30>; + resets = <&reset TIM4_RESET>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + resets = <&reset TIM5_RESET>; + clocks = <&clk_pmtr1>; + }; + + timer6: timer@40001000 { + compatible = "st,stm32-timer"; + reg = <0x40001000 0x400>; + interrupts = <54>; + resets = <&reset TIM6_RESET>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + timer7: timer@40001400 { + compatible = "st,stm32-timer"; + reg = <0x40001400 0x400>; + interrupts = <55>; + resets = <&reset TIM7_RESET>; + clocks = <&clk_pmtr1>; + + status = "disabled"; + }; + + usart1: usart@40011000 { + compatible = "st,stm32-usart"; + reg = <0x40011000 0x400>; + interrupts = <37>; + clocks = <&clk_pclk2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + + status = "disabled"; + }; + + usart2: usart@40004400 { + compatible = "st,stm32-usart"; + reg = <0x40004400 0x400>; + interrupts = <38>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + + status = "disabled"; + }; + + usart3: usart@40004800 { + compatible = "st,stm32-usart"; + reg = <0x40004800 0x400>; + interrupts = <39>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + + status = "disabled"; + }; + + usart4: usart@40004c00 { + compatible = "st,stm32-usart"; + reg = <0x40004c00 0x400>; + interrupts = <52>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + + status = "disabled"; + }; + + usart5: usart@40005000 { + compatible = "st,stm32-usart"; + reg = <0x40005000 0x400>; + interrupts = <53>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + + status = "disabled"; + }; + + usart6: usart@40011400 { + compatible = "st,stm32-usart"; + reg = <0x40011400 0x400>; + interrupts = <71>; + clocks = <&clk_pclk2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + + status = "disabled"; + }; + + usart7: usart@40007800 { + compatible = "st,stm32-usart"; + reg = <0x40007800 0x400>; + interrupts = <82>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + + status = "disabled"; + }; + + usart8: usart@40007c00 { + compatible = "st,stm32-usart"; + reg = <0x40007c00 0x400>; + interrupts = <83>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + + status = "disabled"; + }; + }; +};