| Message ID | 1425242887-7594-3-git-send-email-rvolkov@v1ros.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi index a1a854b..e9ef539 100644 --- a/arch/arm/boot/dts/wm8505.dtsi +++ b/arch/arm/boot/dts/wm8505.dtsi @@ -281,8 +281,8 @@ sdhc@d800a000 { compatible = "wm,wm8505-sdhc"; - reg = <0xd800a000 0x1000>; - interrupts = <20 21>; + reg = <0xd800a000 0x400>; + interrupts = <20>, <21>; clocks = <&clksdhc>; bus-width = <4>; };
According to datasheet, the registers space of SDHC controller is 1Kb, not '0x1000', the correct value should be '0x400'. Bracket interrupt numbers individually per recommendations. Signed-off-by: Roman Volkov <rvolkov@v1ros.org> --- arch/arm/boot/dts/wm8505.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)