| Message ID | 1425479753-18349-7-git-send-email-alex.bennee@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 4 March 2015 at 23:35, Alex Bennée <alex.bennee@linaro.org> wrote: > I was getting very confused about the duplication of state. Perhaps we > should just get rid of env->spsr and use helpers that understand the > banking? Doesn't seem worth changing the current working code to something else that's strictly less efficient... spsr is by no means the only banked-by-mode register, and it works just like all the others. -- PMM
Peter Maydell <peter.maydell@linaro.org> writes: > On 4 March 2015 at 23:35, Alex Bennée <alex.bennee@linaro.org> wrote: >> I was getting very confused about the duplication of state. Perhaps we >> should just get rid of env->spsr and use helpers that understand the >> banking? > > Doesn't seem worth changing the current working code to something > else that's strictly less efficient... spsr is by no means the > only banked-by-mode register, and it works just like all the others. Fair enough. I just wanted to make it clear it was a cached value for the benefit of TCG. > > -- PMM
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 11845a6..d7fd13f 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -155,6 +155,11 @@ typedef struct CPUARMState { This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ uint32_t uncached_cpsr; + /* The spsr is a alias for spsr_elN where N is the current + * exception level. It is provided for here so the TCG msr/mrs + * implementation can access one register. Care needs to be taken + * to ensure the banked_spsr[] is also updated. + */ uint32_t spsr; /* Banked registers. */
I was getting very confused about the duplication of state. Perhaps we should just get rid of env->spsr and use helpers that understand the banking? Signed-off-by: Alex Bennée <alex.bennee@linaro.org>