From patchwork Wed Mar 11 14:12:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 5985501 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E1D1ABF440 for ; Wed, 11 Mar 2015 14:16:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DD27920351 for ; Wed, 11 Mar 2015 14:16:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C60DD2013D for ; Wed, 11 Mar 2015 14:15:59 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YVhOL-0002Rt-Gn; Wed, 11 Mar 2015 14:13:45 +0000 Received: from mail-lb0-f180.google.com ([209.85.217.180]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YVhNb-0001gy-E2 for linux-arm-kernel@lists.infradead.org; Wed, 11 Mar 2015 14:13:00 +0000 Received: by lbvp9 with SMTP id p9so9105568lbv.8 for ; Wed, 11 Mar 2015 07:12:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pQfuf44hx47GqmG9VGXQO7iNjvuebQTOOxm+4MkrvO0=; b=l5axWDqyXraQiLCEX7Ua3DEAPg/JV6pz0hbcfEXylbbdpQmkPX4gBv53CgF7DTQ6mh szGQVbQcJ8YmGJ2lpPe0EQ4B6xrsriSMmMvzlZ86e7PqLmgYeqmGDw8WIUHKl90v09H4 sWKxjxRtJ9CDlRXGkobxP6q8M00/OICvnr55mBXlhZurzzB5QlN6wpvxO7Qd4hqo74bl l/XsmtHsrvwRR/e7s+AHMb0OmPkOPN28kRkg6IBRk4q6GpwYLM/CgtnjKZS9iohTURyt HQuqX31VVPndE3kPMtocpgIeRKVTYkXtNl7PWqCsuOB1zE3NC6TE0AzoiLz6wyUFfT9y amew== X-Gm-Message-State: ALoCoQk1FqVo0N3nbOf9aad/PH44jtHCzounp0ZQAQPji4YNYdxRub0ZQifjIHx1ifpMB9vc9uoX X-Received: by 10.112.114.164 with SMTP id jh4mr34967563lbb.21.1426083157111; Wed, 11 Mar 2015 07:12:37 -0700 (PDT) Received: from tn-HP-4.semihalf.com (cardhu.semihalf.com. [213.17.239.108]) by mx.google.com with ESMTPSA id x4sm746600lba.22.2015.03.11.07.12.33 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Mar 2015 07:12:36 -0700 (PDT) From: Tomasz Nowicki To: bhelgaas@google.com, wangyijing@huawei.com, arnd@arndb.de, hanjun.guo@linaro.org, Liviu.Dudau@arm.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, rjw@rjwysocki.net, al.stone@linaro.org Subject: [PATCH v4 2/9] x86, pci: Abstract PCI config accessors and use AMD Fam10h workaround exclusively. Date: Wed, 11 Mar 2015 15:12:42 +0100 Message-Id: <1426083169-8698-3-git-send-email-tomasz.nowicki@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1426083169-8698-1-git-send-email-tomasz.nowicki@linaro.org> References: <1426083169-8698-1-git-send-email-tomasz.nowicki@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150311_071259_715538_E5553900 X-CRM114-Status: GOOD ( 13.94 ) X-Spam-Score: -0.7 (/) Cc: linaro-acpi@lists.linaro.org, linux-pci@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, Tomasz Nowicki , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From now on, readb()/writeb()/etc. generic calls are used as default approach. Special MMIO accessors are registered for AMD Fam10h CPUs only. Signed-off-by: Tomasz Nowicki --- arch/x86/include/asm/pci_x86.h | 8 +++ arch/x86/pci/mmconfig-shared.c | 114 +++++++++++++++++++++++++++++++++++++++++ arch/x86/pci/mmconfig_32.c | 24 +-------- arch/x86/pci/mmconfig_64.c | 24 +-------- arch/x86/pci/numachip.c | 24 +-------- 5 files changed, 128 insertions(+), 66 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index d024f4d..c57c225 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -137,6 +137,11 @@ struct pci_mmcfg_region { char name[PCI_MMCFG_RESOURCE_NAME_LEN]; }; +struct pci_mmcfg_mmio_ops { + u32 (*read)(int len, void __iomem *addr); + void (*write)(int len, void __iomem *addr, u32 value); +}; + extern int __init pci_mmcfg_arch_init(void); extern void __init pci_mmcfg_arch_free(void); extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); @@ -145,6 +150,9 @@ extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, phys_addr_t addr); extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); +extern u32 pci_mmio_read(int len, void __iomem *addr); +extern void pci_mmio_write(int len, void __iomem *addr, u32 value); +extern void pci_mmconfig_register_mmio(struct pci_mmcfg_mmio_ops *ops); extern struct list_head pci_mmcfg_list; diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index dd30b7e..8b3bc4f 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -31,6 +31,118 @@ static DEFINE_MUTEX(pci_mmcfg_lock); LIST_HEAD(pci_mmcfg_list); +static u32 +pci_mmconfig_generic_read(int len, void __iomem *addr) +{ + u32 data = 0; + + switch (len) { + case 1: + data = readb(addr); + break; + case 2: + data = readw(addr); + break; + case 4: + data = readl(addr); + break; + } + + return data; +} + +static void +pci_mmconfig_generic_write(int len, void __iomem *addr, u32 value) +{ + switch (len) { + case 1: + writeb(value, addr); + break; + case 2: + writew(value, addr); + break; + case 4: + writel(value, addr); + break; + } +} + +static struct pci_mmcfg_mmio_ops pci_mmcfg_mmio_default = { + .read = pci_mmconfig_generic_read, + .write = pci_mmconfig_generic_write, +}; + +static struct pci_mmcfg_mmio_ops *pci_mmcfg_mmio = &pci_mmcfg_mmio_default; + +static u32 +pci_mmconfig_amd_read(int len, void __iomem *addr) +{ + u32 data = 0; + + switch (len) { + case 1: + data = mmio_config_readb(addr); + break; + case 2: + data = mmio_config_readw(addr); + break; + case 4: + data = mmio_config_readl(addr); + break; + } + + return data; +} + +static void +pci_mmconfig_amd_write(int len, void __iomem *addr, u32 value) +{ + switch (len) { + case 1: + mmio_config_writeb(addr, value); + break; + case 2: + mmio_config_writew(addr, value); + break; + case 4: + mmio_config_writel(addr, value); + break; + } +} + +static struct pci_mmcfg_mmio_ops pci_mmcfg_mmio_amd_fam10h = { + .read = pci_mmconfig_amd_read, + .write = pci_mmconfig_amd_write, +}; + +void +pci_mmconfig_register_mmio(struct pci_mmcfg_mmio_ops *ops) +{ + pci_mmcfg_mmio = ops; +} + +u32 +pci_mmio_read(int len, void __iomem *addr) +{ + if (!pci_mmcfg_mmio) { + pr_err("PCI config space has no accessors !"); + return 0; + } + + return pci_mmcfg_mmio->read(len, addr); +} + +void +pci_mmio_write(int len, void __iomem *addr, u32 value) +{ + if (!pci_mmcfg_mmio) { + pr_err("PCI config space has no accessors !"); + return; + } + + pci_mmcfg_mmio->write(len, addr, value); +} + static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) { if (cfg->res.parent) @@ -231,6 +343,8 @@ static const char *__init pci_mmcfg_amd_fam10h(void) return NULL; } + pci_mmconfig_register_mmio(&pci_mmcfg_mmio_amd_fam10h); + return "AMD Family 10h NB"; } diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c index 43984bc..4b3d025 100644 --- a/arch/x86/pci/mmconfig_32.c +++ b/arch/x86/pci/mmconfig_32.c @@ -71,17 +71,7 @@ err: *value = -1; pci_exp_set_dev_base(base, bus, devfn); - switch (len) { - case 1: - *value = mmio_config_readb(mmcfg_virt_addr + reg); - break; - case 2: - *value = mmio_config_readw(mmcfg_virt_addr + reg); - break; - case 4: - *value = mmio_config_readl(mmcfg_virt_addr + reg); - break; - } + *value = pci_mmio_read(len, mmcfg_virt_addr + reg); raw_spin_unlock_irqrestore(&pci_config_lock, flags); rcu_read_unlock(); @@ -108,17 +98,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, pci_exp_set_dev_base(base, bus, devfn); - switch (len) { - case 1: - mmio_config_writeb(mmcfg_virt_addr + reg, value); - break; - case 2: - mmio_config_writew(mmcfg_virt_addr + reg, value); - break; - case 4: - mmio_config_writel(mmcfg_virt_addr + reg, value); - break; - } + pci_mmio_write(len, mmcfg_virt_addr + reg, value); raw_spin_unlock_irqrestore(&pci_config_lock, flags); rcu_read_unlock(); diff --git a/arch/x86/pci/mmconfig_64.c b/arch/x86/pci/mmconfig_64.c index bea5249..032593d 100644 --- a/arch/x86/pci/mmconfig_64.c +++ b/arch/x86/pci/mmconfig_64.c @@ -42,17 +42,7 @@ err: *value = -1; goto err; } - switch (len) { - case 1: - *value = mmio_config_readb(addr + reg); - break; - case 2: - *value = mmio_config_readw(addr + reg); - break; - case 4: - *value = mmio_config_readl(addr + reg); - break; - } + *value = pci_mmio_read(len, addr + reg); rcu_read_unlock(); return 0; @@ -74,17 +64,7 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, return -EINVAL; } - switch (len) { - case 1: - mmio_config_writeb(addr + reg, value); - break; - case 2: - mmio_config_writew(addr + reg, value); - break; - case 4: - mmio_config_writel(addr + reg, value); - break; - } + pci_mmio_write(len, addr + reg, value); rcu_read_unlock(); return 0; diff --git a/arch/x86/pci/numachip.c b/arch/x86/pci/numachip.c index 2e565e6..5047e9b 100644 --- a/arch/x86/pci/numachip.c +++ b/arch/x86/pci/numachip.c @@ -51,17 +51,7 @@ err: *value = -1; goto err; } - switch (len) { - case 1: - *value = mmio_config_readb(addr + reg); - break; - case 2: - *value = mmio_config_readw(addr + reg); - break; - case 4: - *value = mmio_config_readl(addr + reg); - break; - } + *value = pci_mmio_read(len, addr + reg); rcu_read_unlock(); return 0; @@ -87,17 +77,7 @@ static int pci_mmcfg_write_numachip(unsigned int seg, unsigned int bus, return -EINVAL; } - switch (len) { - case 1: - mmio_config_writeb(addr + reg, value); - break; - case 2: - mmio_config_writew(addr + reg, value); - break; - case 4: - mmio_config_writel(addr + reg, value); - break; - } + pci_mmio_write(len, addr + reg, value); rcu_read_unlock(); return 0;