From patchwork Thu Mar 12 12:15:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 5994011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 969B59F2A9 for ; Thu, 12 Mar 2015 12:32:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AD790200ED for ; Thu, 12 Mar 2015 12:32:34 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C89B220155 for ; Thu, 12 Mar 2015 12:32:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YW2FG-0004JR-2Z; Thu, 12 Mar 2015 12:29:46 +0000 Received: from hqemgate16.nvidia.com ([216.228.121.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YW22G-0007XX-ST for linux-arm-kernel@lists.infradead.org; Thu, 12 Mar 2015 12:16:23 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 12 Mar 2015 05:16:24 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 12 Mar 2015 05:14:17 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 12 Mar 2015 05:14:17 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.342.0; Thu, 12 Mar 2015 05:15:51 -0700 Received: from vinceh-linux.nvidia.com (Not Verified[10.19.108.63]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 12 Mar 2015 05:15:51 -0700 From: Vince Hsu To: thierry.reding@gmail.com, pdeschrijver@nvidia.com, swarren@wwwdotorg.org, gnurou@gmail.com, jroedel@suse.de, p.zabel@pengutronix.de, mturquette@linaro.org, pgaikwad@nvidia.com, sboyd@codeaurora.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tbergstrom@nvidia.com, airlied@linux.ie, bhelgaas@google.com, tj@kernel.org, arnd@arndb.de, robh@kernel.org, will.deacon@arm.com Subject: [PATCH v2 08/17] ARM: tegra: add PM domain device nodes to Tegra30 DT Date: Thu, 12 Mar 2015 20:15:09 +0800 Message-ID: <1426162518-7405-9-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> References: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150312_051622_304295_0C22ADA9 X-CRM114-Status: GOOD ( 10.90 ) X-Spam-Score: -5.0 (-----) Cc: devicetree@vger.kernel.org, Vince Hsu , linux-pm@vger.kernel.org, viresh.kumar@linaro.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Also bind the PM domain provider and consumer together. Signed-off-by: Vince Hsu --- arch/arm/boot/dts/tegra30.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index db4810df142c..bec1b17fdcab 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -2,6 +2,7 @@ #include #include #include +#include #include #include "skeleton.dtsi" @@ -36,6 +37,7 @@ 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ + power-domains = <&pmc TEGRA_POWERGATE_PCIE>; clocks = <&tegra_car TEGRA30_CLK_PCIE>, <&tegra_car TEGRA30_CLK_AFI>, <&tegra_car TEGRA30_CLK_PLL_E>, @@ -149,6 +151,14 @@ gr3d@54180000 { compatible = "nvidia,tegra30-gr3d"; reg = <0x54180000 0x00040000>; + /* + * Actually the gr3d has two power domains, but the + * generic power domain doesn't support multiple + * domain provider for one device yet. So we claim + * the gr3d is powered by the domain 3D1 here, and + * let the 3D1 depend on 3D below. + */ + power-domains = <&pmc TEGRA_POWERGATE_3D1>; clocks = <&tegra_car TEGRA30_CLK_GR3D &tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; @@ -613,11 +623,44 @@ status = "disabled"; }; - pmc@7000e400 { + pmc: pmc@7000e400 { compatible = "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #power-domain-cells = <1>; + }; + + gr3dpd: gr3d-power-domain { + compatible = "nvidia,power-domains"; + name = "gr3d-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA30_CLK_GR3D>; + resets = <&tegra_car 24>; + nvidia,swgroup = <&mc TEGRA_SWGROUP_NV>; + }; + + gr3d2-power-domain { + compatible = "nvidia,power-domains"; + name = "gr3d2-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA30_CLK_GR3D2>; + resets = <&tegra_car 98>; + nvidia,swgroup = <&mc TEGRA_SWGROUP_NV2>; + depend-on = <&gr3dpd>; + }; + + pcie-power-domain { + compatible = "nvidia,power-domains"; + name = "pcie-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA30_CLK_AFI>, + <&tegra_car TEGRA30_CLK_PCIE>, + <&tegra_car TEGRA30_CLK_CML0>; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + nvidia,swgroup = <&mc TEGRA_SWGROUP_AFI>; }; mc: memory-controller@7000f000 {