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[resend] ASoC: fsl-ssi: Fix bitclock calculation for master mode

Message ID 1427121972-5059-1-git-send-email-mkl@pengutronix.de (mailing list archive)
State New, archived
Headers show

Commit Message

Marc Kleine-Budde March 23, 2015, 2:46 p.m. UTC 
From: Sascha Hauer <s.hauer@pengutronix.de>

in fsl_ssi_set_bclk we are looking for the best divider by iterating
over all possible dividers. The divider is in the range 1..256, so
make this clear by using 'div' as name for the loop counter and iterate
from 1 to 256 instead of 0 to 255. This makes obvious that tmprate is
calculated wrong, it has to be freq * factor * div, not
freq * factor * (i + 2).

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
 sound/soc/fsl/fsl_ssi.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Mark Brown March 25, 2015, 4:58 p.m. UTC | #1 
On Mon, Mar 23, 2015 at 03:46:12PM +0100, Marc Kleine-Budde wrote:
> From: Sascha Hauer <s.hauer@pengutronix.de>
> 
> in fsl_ssi_set_bclk we are looking for the best divider by iterating
> over all possible dividers. The divider is in the range 1..256, so

This doesn't apply against current code, please check and resend.
Marc Kleine-Budde March 25, 2015, 9:44 p.m. UTC | #2 
On 03/25/2015 05:58 PM, Mark Brown wrote:
> On Mon, Mar 23, 2015 at 03:46:12PM +0100, Marc Kleine-Budde wrote:
>> From: Sascha Hauer <s.hauer@pengutronix.de>
>>
>> in fsl_ssi_set_bclk we are looking for the best divider by iterating
>> over all possible dividers. The divider is in the range 1..256, so
> 
> This doesn't apply against current code, please check and resend.

The problem has been fixed by:

    6c8ca30eec7b ASoC: fsl_ssi: Don't try to round-up for PM divisor
                 calculation

in the meantime.

Marc
diff mbox

Patch

diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
index b9fabbf69db6..b8af08e49085 100644
--- a/sound/soc/fsl/fsl_ssi.c
+++ b/sound/soc/fsl/fsl_ssi.c
@@ -578,7 +578,7 @@  static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 	struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
 	struct regmap *regs = ssi_private->regs;
 	int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
-	u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
+	u32 pm = 999, div2, psr, stccr, mask, afreq, factor, div;
 	unsigned long clkrate, baudrate, tmprate;
 	u64 sub, savesub = 100000;
 	unsigned int freq;
@@ -602,8 +602,8 @@  static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 
 	factor = (div2 + 1) * (7 * psr + 1) * 2;
 
-	for (i = 0; i < 255; i++) {
-		tmprate = freq * factor * (i + 2);
+	for (div = 1; div < 256; div++) {
+		tmprate = freq * factor * div;
 
 		if (baudclk_is_used)
 			clkrate = clk_get_rate(ssi_private->baudclk);
@@ -618,7 +618,7 @@  static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 			continue;
 
 		clkrate /= factor;
-		afreq = clkrate / (i + 1);
+		afreq = clkrate / div;
 
 		if (freq == afreq)
 			sub = 0;
@@ -636,7 +636,7 @@  static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
 		if (sub < savesub) {
 			baudrate = tmprate;
 			savesub = sub;
-			pm = i;
+			pm = div - 1;
 		}
 
 		/* We are lucky */