From patchwork Fri Mar 27 15:57:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 6109281 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CE4BD9F2A9 for ; Fri, 27 Mar 2015 16:01:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B6ABF2041E for ; Fri, 27 Mar 2015 16:01:07 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B76D1203EC for ; Fri, 27 Mar 2015 16:01:06 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YbWeH-0001WV-NZ; Fri, 27 Mar 2015 15:58:17 +0000 Received: from mailout4.w1.samsung.com ([210.118.77.14]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YbWeC-0001PE-Jr for linux-arm-kernel@lists.infradead.org; Fri, 27 Mar 2015 15:58:14 +0000 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NLV00ILAOIW4VB0@mailout4.w1.samsung.com> for linux-arm-kernel@lists.infradead.org; Fri, 27 Mar 2015 16:01:44 +0000 (GMT) X-AuditID: cbfec7f5-b7fc86d0000066b7-a3-55157dfa9e9d Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id A4.F3.26295.AFD75155; Fri, 27 Mar 2015 15:57:46 +0000 (GMT) Received: from AMDC1943.digital.local ([106.116.151.171]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NLV00GLLOC76R80@eusync2.samsung.com>; Fri, 27 Mar 2015 15:57:47 +0000 (GMT) From: Krzysztof Kozlowski To: Jingoo Han , Inki Dae , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , David Airlie , Kukjin Kim , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [RFT PATCH] drm/exynos: Enable DP clock to fix display on Exynos5250 and other Date: Fri, 27 Mar 2015 16:57:36 +0100 Message-id: <1427471856-20918-1-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBLMWRmVeSWpSXmKPExsVy+t/xK7q/akVDDSbNkrS4te4cq0XvuZNM Fle+vmezmHR/AovF0d8FFpcXXmK1eHHvIovF6xeGFv2PXzNbnG16w26x6fE1VosTfR9YLS7v msNmMeP8PiaLtUfuslss2PiI0WLG5JdsDoIef59fZ/HYtKqTzWP7twesHve7jzN5bF5S79G3 ZRWjx+dNcgHsUVw2Kak5mWWpRfp2CVwZLZ92MhasU664+3clSwPjNdkuRg4OCQETia558V2M nECmmMSFe+vZuhi5OIQEljJKPFx9iRHC6WOS+PigmRGkik3AWGLz8iVgVSICm5klXjzfCFbF LHCXUeLV/JNgVcICkRLbHx5nBrFZBFQlls9+xQRi8wq4S0w+MI0ZYp+cxMljk1knMHIvYGRY xSiaWppcUJyUnmukV5yYW1yal66XnJ+7iRESml93MC49ZnWIUYCDUYmHl7NeJFSINbGsuDL3 EKMEB7OSCO+6AtFQId6UxMqq1KL8+KLSnNTiQ4xMHJxSDYypC598k5FK/mee89Tc5sSsO7aX py+NWvOtJ2MF0297K2Xp/383JOUxbbq9VC3pvLCxSNuk/z0cpzfNEFsQJKfznttQ4WuHXfnn 6wmfb11e0dIk+tqoNXl2+On2GDHdf1XvwoW1907qe1Y8Leu/s/TJ/IiXq42VPp1WZ1qd0nSp gH/KKb/vnVlKLMUZiYZazEXFiQAUj1nIKwIAAA== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150327_085812_844987_A1664896 X-CRM114-Status: GOOD ( 11.24 ) X-Spam-Score: -5.0 (-----) Cc: Andrzej Hajda , Krzysztof Kozlowski , Javier Martinez Canillas , stable@vger.kernel.org, Marek Szyprowski X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP After adding display power domain for Exynos5250 in commit 2d2c9a8d0a4f ("ARM: dts: add display power domain for exynos5250") the display on Chromebook Snow and others stopped working after boot. The reason for this suggested Andrzej Hajda: the DP clock was disabled. This clock is required by Display Port and is enabled by bootloader. However when FIMD driver probing was deferred, the display power domain was turned off. This effectively reset the value of DP clock enable register. When exynos-dp is later probed, the clock is not enabled and display is not properly configured: exynos-dp 145b0000.dp-controller: Timeout of video streamclk ok exynos-dp 145b0000.dp-controller: unable to config video Signed-off-by: Krzysztof Kozlowski Reported-by: Javier Martinez Canillas Fixes: 2d2c9a8d0a4f ("ARM: dts: add display power domain for exynos5250") Cc: --- This should fix issue reported by Javier [1][2]. Tested on Chromebook Snow (Exynos 5250). More testing would be great, especially on other Exynos 5xxx products. [1] http://thread.gmane.org/gmane.linux.kernel.samsung-soc/43889 [2] http://thread.gmane.org/gmane.linux.ports.arm.kernel/400290 --- drivers/gpu/drm/exynos/exynos_dp_core.c | 10 ++++++++++ drivers/gpu/drm/exynos/exynos_drm_fimd.c | 19 +++++++++++++++++++ include/video/samsung_fimd.h | 6 ++++++ 3 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c index bf17a60b40ed..1dbfba58f909 100644 --- a/drivers/gpu/drm/exynos/exynos_dp_core.c +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c @@ -32,10 +32,16 @@ #include #include "exynos_dp_core.h" +#include "exynos_drm_fimd.h" #define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \ connector) +static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp) +{ + return to_exynos_crtc(dp->encoder->crtc); +} + static inline struct exynos_dp_device * display_to_dp(struct exynos_drm_display *d) { @@ -1070,6 +1076,8 @@ static void exynos_dp_poweron(struct exynos_dp_device *dp) } } + fimd_dp_clock_enable(dp_to_crtc(dp), true); + clk_prepare_enable(dp->clock); exynos_dp_phy_init(dp); exynos_dp_init_dp(dp); @@ -1094,6 +1102,8 @@ static void exynos_dp_poweroff(struct exynos_dp_device *dp) exynos_dp_phy_exit(dp); clk_disable_unprepare(dp->clock); + fimd_dp_clock_enable(dp_to_crtc(dp), false); + if (dp->panel) { if (drm_panel_unprepare(dp->panel)) DRM_ERROR("failed to turnoff the panel\n"); diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index c300e22da8ac..bdf0818dc8f5 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -32,6 +32,7 @@ #include "exynos_drm_fbdev.h" #include "exynos_drm_crtc.h" #include "exynos_drm_iommu.h" +#include "exynos_drm_fimd.h" /* * FIMD stands for Fully Interactive Mobile Display and @@ -1231,6 +1232,24 @@ static int fimd_remove(struct platform_device *pdev) return 0; } +void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) +{ + struct fimd_context *ctx = crtc->ctx; + u32 val; + + /* + * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE + * clock. On these SoCs the bootloader may enable it but any + * power domain off/on will reset it to disable state. + */ + if (ctx->driver_data != &exynos5_fimd_driver_data) + return; + + val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; + writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); +} +EXPORT_SYMBOL_GPL(fimd_dp_clock_enable); + struct platform_driver fimd_driver = { .probe = fimd_probe, .remove = fimd_remove, diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h index a20e4a3a8b15..847a0a2b399c 100644 --- a/include/video/samsung_fimd.h +++ b/include/video/samsung_fimd.h @@ -436,6 +436,12 @@ #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) +/* Display port clock control */ +#define DP_MIE_CLKCON 0x27c +#define DP_MIE_CLK_DISABLE 0x0 +#define DP_MIE_CLK_DP_ENABLE 0x2 +#define DP_MIE_CLK_MIE_ENABLE 0x3 + /* Notes on per-window bpp settings * * Value Win0 Win1 Win2 Win3 Win 4