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X-Spam-Score: -0.0 (/) Cc: bhupesh.sharma@freescale.com, Catalin.Marinas@arm.com, will.deacon@arm.com, stuart.yoder@freescale.com, olof@lixom.net, bhupesh.linux@gmail.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch updates the 'clk-qoriq' device-tree bindings for chassis-3.0 compliant SoCs from FSL, for e.g. LS2085A Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/clock/qoriq-clock.txt | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index df4a259..60d758e 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -14,6 +14,7 @@ Chassis Version Example Chips --------------- ------------- 1.0 p4080, p5020, p5040 2.0 t4240, b4860, t1040 +3.0 ls2085a 1. Clock Block Binding @@ -30,9 +31,11 @@ Required properties: * "fsl,b4420-clockgen" * "fsl,b4860-clockgen" * "fsl,ls1021a-clockgen" + * "fsl,ls2085a-clockgen" Chassis clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks + * "fsl,qoriq-clockgen-3.0": for chassis 3.0 clocks - reg: Describes the address of the device's resources within the address space defined by its parent bus, and resource zero represents the clock register set @@ -57,18 +60,23 @@ Required properties: - compatible : Should include one of the following: * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) + * "fsl,qoriq-core-pll-3.0" for core PLL clocks (v3.0) * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) + * "fsl,qoriq-core-mux-3.0" for core mux clocks (v3.0) * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). It takes parent's clock-frequency as its clock. * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). It takes parent's clock-frequency as its clock. + * "fsl,qoriq-sysclk-3.0": for input system clock (v3.0). + It takes parent's clock-frequency as its clock. * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) + * "fsl,qoriq-platform-pll-3.0" for the platform PLL clock (v3.0) - #clock-cells: From common clock binding. The number of cells in a - clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" - clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. - For "fsl,qoriq-core-pll-[1,2].0" clocks, the single + clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2,3].0" + clocks, or <1> for "fsl,qoriq-core-pll-[1,2,3].0" clocks. + For "fsl,qoriq-core-pll-[1,2,3].0" clocks, the single clock-specifier cell may take the following values: * 0 - equal to the PLL frequency * 1 - equal to the PLL frequency divided by 2