From patchwork Fri Apr 10 09:12:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel FERNANDEZ X-Patchwork-Id: 6193771 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D7C8BBF4A6 for ; Fri, 10 Apr 2015 09:19:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 00FCF203A0 for ; Fri, 10 Apr 2015 09:19:23 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 10F1020160 for ; Fri, 10 Apr 2015 09:19:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YgV28-0003JN-2p; Fri, 10 Apr 2015 09:15:28 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YgV13-0001WC-Eb for linux-arm-kernel@lists.infradead.org; Fri, 10 Apr 2015 09:14:23 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id t3A90vwU008508; Fri, 10 Apr 2015 11:13:24 +0200 Received: from beta.dmz-us.st.com (beta.dmz-us.st.com [167.4.1.35]) by mx08-00178001.pphosted.com with ESMTP id 1tngnrys0p-1 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 10 Apr 2015 11:13:24 +0200 Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id AC8BC2B; Fri, 10 Apr 2015 09:13:04 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 03B146DE; Fri, 10 Apr 2015 09:12:57 +0000 (GMT) Received: from lmenx315.lme.st.com ([10.48.254.84]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BZT47597 (AUTH frq07381); Fri, 10 Apr 2015 11:12:41 +0200 From: Gabriel FERNANDEZ To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Bjorn Helgaas , Jingoo Han , Lucas Stach , Fabrice Gasnier , Kishon Vijay Abraham I , Andrew Morton , " David S. Miller" , Greg KH , Mauro Carvalho Chehab , Joe Perches , Tejun Heo , Arnd Bergmann , Viresh Kumar , Thierry Reding , Phil Edworthy , Minghuan Lian , Tanmay Inamdar , , Sachin Kamat , Andrew Lunn , Liviu Dudau Subject: [PATCH v3 2/5] PCI: st: Add Device Tree bindings for sti pcie Date: Fri, 10 Apr 2015 11:12:45 +0200 Message-Id: <1428657168-12495-3-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1428657168-12495-1-git-send-email-gabriel.fernandez@linaro.org> References: <1428657168-12495-1-git-send-email-gabriel.fernandez@linaro.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.13.68, 1.0.33, 0.0.0000 definitions=2015-04-10_02:2015-04-09, 2015-04-10, 1970-01-01 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150410_021421_830088_D49EC78D X-CRM114-Status: GOOD ( 13.72 ) X-Spam-Score: -0.7 (/) Cc: devicetree@vger.kernel.org, kernel@stlinux.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Gabriel Fernandez , Lee Jones , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier Signed-off-by: Gabriel Fernandez --- Documentation/devicetree/bindings/pci/st-pcie.txt | 53 +++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt b/Documentation/devicetree/bindings/pci/st-pcie.txt new file mode 100644 index 0000000..25fcab3 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt @@ -0,0 +1,53 @@ +STMicroelectronics STi PCIe controller + +This PCIe host controller is based on the Synopsis Designware PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: + - compatible: "st,stih407-pcie" + - reg: base address and length of the pcie controller, mem-window address + and length available to the controller. + - interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. + - interrupt-names: Should be "msi". STi interrupt that is asserted when an + MSI is received. + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg + offset for IP configuration. + - resets, reset-names: the power-down and soft-reset lines of PCIe IP. + Associated names must be "powerdown" and "softreset". + - phys, phy-names: the phandle for the PHY device. + Associated name must be "pcie" + +Optional properties: + - reset-gpio: a GPIO spec to define which pin is connected to the bus reset. + +Example: + +pcie0: pcie@9b00000 { + compatible = "st,pcie", "snps,dw-pcie"; + device_type = "pci"; + reg = <0x09b00000 0x4000>, /* dbi cntrl registers */ + <0x2fff0000 0x00010000>, /* configuration space */ + <0x40000000 0x80000000>; /* lmi mem window */ + reg-names = "dbi", "config", "mem-window"; + st,syscfg = <&syscfg_core 0xd8 0xe0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x82000000 0 0x20000000 0x20000000 0 0x0FFF0000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT A */ + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT B */ + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT C */ + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT D */ + + resets = <&powerdown STIH407_PCIE0_POWERDOWN>, + <&softreset STIH407_PCIE0_SOFTRESET>; + reset-names = "powerdown", + "softreset"; + phys = <&phy_port0 PHY_TYPE_PCIE>; + phy-names = "pcie"; +};