From patchwork Mon Apr 13 09:17:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bintian Wang X-Patchwork-Id: 6206831 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 046959F398 for ; Mon, 13 Apr 2015 09:22:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1A9382026F for ; Mon, 13 Apr 2015 09:22:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8436E201BB for ; Mon, 13 Apr 2015 09:22:23 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YhaXK-0000ss-5y; Mon, 13 Apr 2015 09:20:10 +0000 Received: from szxga02-in.huawei.com ([119.145.14.65]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YhaWl-00007N-9L for linux-arm-kernel@lists.infradead.org; Mon, 13 Apr 2015 09:19:37 +0000 Received: from 172.24.2.119 (EHLO SZXEML429-HUB.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CJS06140; Mon, 13 Apr 2015 17:14:18 +0800 (CST) Received: from localhost.localdomain (10.110.52.31) by SZXEML429-HUB.china.huawei.com (10.82.67.184) with Microsoft SMTP Server id 14.3.158.1; Mon, 13 Apr 2015 17:14:01 +0800 From: Bintian Wang To: , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 2/6] arm64: hi6220: Document devicetree bindings for Hisilicon hi6220 SoC Date: Mon, 13 Apr 2015 17:17:36 +0800 Message-ID: <1428916660-25910-3-git-send-email-bintian.wang@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1428916660-25910-1-git-send-email-bintian.wang@huawei.com> References: <1428916660-25910-1-git-send-email-bintian.wang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.110.52.31] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150413_021935_723477_71C47FB7 X-CRM114-Status: UNSURE ( 8.36 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.3 (--) Cc: dan.zhao@hisilicon.com, huxinwei@huawei.com, bintian.wang@huawei.com, xuyiping@hisilicon.com, victor.lixin@hisilicon.com, btw@mail.itp.ac.cn, puck.chen@hisilicon.com, wangbinghui@hisilicon.com, zhenwei.wang@hisilicon.com, liguozhu@hisilicon.com, kong.kongxinwei@hisilicon.com, heyunlei@huawei.com, w.f@huawei.com, z.liuxinliang@huawei.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds documentation for the devicetree bindings used by the DT files of Hisilicon hi6220 SoC mobile platform. Signed-off-by: Bintian Wang --- .../bindings/arm/hisilicon/hisilicon.txt | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 35b1bd4..66ad65d 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -13,6 +13,9 @@ HiP01 ca9x2 Board Required root node properties: - compatible = "hisilicon,hip01-ca9x2"; +HiKey Board +Required root node properties: + - compatible = "hisilicon,hi6220-hikey"; Hisilicon system controller @@ -29,6 +32,10 @@ Optional properties: - resume-offset : offset in sysctrl for notifying cpu0 when resume - reboot-offset : offset in sysctrl for system reboot +For some SoCs(e.g. Hi6220), many clock registers are defined under this +controller, so "#clock-cells" is a required property for these SoCs and +it should be set to 1. + Example: /* for Hi3620 */ @@ -40,6 +47,72 @@ Example: reboot-offset = <0x4>; }; + +Hisilicon Power Always ON domain controller + +Hisilicon designs this system controller to control the power always +on domain for mobile platform. + +Required properties: +- compatible : "hisilicon,aoctrl" +- reg : Register address and size + +For some SoCs(e.g. Hi6220), many clock registers are defined under this +controller, so "#clock-cells" is a required property for these SoCs and +it should be set to 1. + +Example: + /*for Hi6220*/ + ao_ctrl: ao_ctrl { + compatible = "hisilicon,aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; + + +Hisilicon Media domain controller + +Hisilicon designs this system controller to control the multimedia +domain(e.g. codec, G3D ...) for mobile platform. + +Required properties: +- compatible : "hisilicon,mediactrl" +- reg : Register address and size + +For some SoCs(e.g. Hi6220), many clock registers are defined under this +controller, so "#clock-cells" is a required property for these SoCs and +it should be set to 1. + +Example: + /*for Hi6220*/ + media_ctrl: media_ctrl { + compatible = "hisilicon,mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + }; + + +Hisilicon Power Management domain controller + +Hisilicon designs this system controller to control the power management +domain for mobile platform. + +Required properties: +- compatible : "hisilicon,pmctrl" +- reg : Register address and size + +For some SoCs (e.g. Hi6220), many clock registers are defined under this +controller, so "#clock-cells" is a required property for these SoCs and +it should be set to 1. + +Example: + /*for Hi6220*/ + pm_ctrl: pm_ctrl { + compatible = "hisilicon,pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; + ----------------------------------------------------------------------- Hisilicon HiP01 system controller