From patchwork Fri Apr 17 08:58:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 6229571 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 86144BF4A6 for ; Fri, 17 Apr 2015 09:06:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8AA6D20260 for ; Fri, 17 Apr 2015 09:06:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 81DBA2025A for ; Fri, 17 Apr 2015 09:06:46 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yj2BN-00082h-CS; Fri, 17 Apr 2015 09:03:29 +0000 Received: from mail-la0-f47.google.com ([209.85.215.47]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yj28C-0004hR-Ip for linux-arm-kernel@lists.infradead.org; Fri, 17 Apr 2015 09:00:13 +0000 Received: by laat2 with SMTP id t2so75211348laa.1 for ; Fri, 17 Apr 2015 01:59:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=quE94EhoGJb96/FG1+Acms+294CT3AZgr8nnQuYQBd8=; b=cYqyHR4BbBIbWCEsFXk32exW8E2OlRrS0zQSIKrOr+6sLlldJF0mTm3FLe+EkntQwq t7HHs/QJQk8aPUxZIA6T+p+xsKCQZL1iwq1wjydG/UMcMOsULAjiiXpDoC0TvPwCVv17 LtOuCvE5g4j95NWc+4cILR3O1tsweuYHJFrJBB9KQh0UQmRAZbqniZz413vQa+7QuWjD 72jMVRGYqCyHNebN1ujmemMlNFeF4Z0B3Cty3zVuguJM1rNCrNhGM1NKZA2+TMryJxvW Q47K0Y7blrMkgFB9IYDdPGkQKo6P2OLWHDOBU0BhbhqlQKie7rjQDJ2HJwctfvZ2Jwyp zaUA== X-Gm-Message-State: ALoCoQnpP/fD1JsXY0yIt0HEfP2UeMxLeTlvx3gcVev6MUq7zokHb+eD6OvR/n6qgqzAv/43NJO6 X-Received: by 10.152.18.225 with SMTP id z1mr1707769lad.124.1429261190007; Fri, 17 Apr 2015 01:59:50 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id f7sm2271119lam.17.2015.04.17.01.59.48 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Apr 2015 01:59:49 -0700 (PDT) From: Linus Walleij To: linux-arm-kernel@lists.infradead.org, Mathieu Poirier Subject: [PATCH 08/13] coresight: etm: retrieve and handle atclk Date: Fri, 17 Apr 2015 10:58:55 +0200 Message-Id: <1429261140-13910-9-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1429261140-13910-1-git-send-email-linus.walleij@linaro.org> References: <1429261140-13910-1-git-send-email-linus.walleij@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150417_020012_862073_1B3FA738 X-CRM114-Status: GOOD ( 17.40 ) X-Spam-Score: -0.7 (/) Cc: Ulf Hansson , "Rafael J. Wysocki" , Russell King , Linus Walleij , Trollkarlen Marklund X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As can be seen from the datasheet of the CoreSight Components, DDI0401C A.1.1 the ETM has a clock signal apart from the AHB interconnect ("amba_pclk", that we're already handling) called ATCLK, ARM Trace Clock, that SoC implementers may provide from an entirely different clock source. So to model this correctly create an optional path for handling ATCLK alongside the PCLK so we don't break old platforms that only define PCLK ("amba_pclk") but still makes it possible for SoCs that have both clock signals (such as the DB8500) to fetch and prepare/enable/disable/ unprepare both clocks. The ATCLK is enabled and disabled using the runtime PM callbacks. Signed-off-by: Linus Walleij Reviewed-by: Ulf Hansson --- drivers/coresight/coresight-etm.h | 2 ++ drivers/coresight/coresight-etm3x.c | 38 ++++++++++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/coresight/coresight-etm.h b/drivers/coresight/coresight-etm.h index d1421e1f8b8a..098ffbec0a44 100644 --- a/drivers/coresight/coresight-etm.h +++ b/drivers/coresight/coresight-etm.h @@ -140,6 +140,7 @@ * struct etm_drvdata - specifics associated to an ETM component * @base: memory mapped base address for this component. * @dev: the device entity associated to this component. + * @atclk: optional clock for the core parts of the ETM. * @csdev: component vitals needed by the framework. * @spinlock: only one at a time pls. * @cpu: the cpu this component is affined to. @@ -191,6 +192,7 @@ struct etm_drvdata { void __iomem *base; struct device *dev; + struct clk *atclk; struct coresight_device *csdev; spinlock_t spinlock; int cpu; diff --git a/drivers/coresight/coresight-etm3x.c b/drivers/coresight/coresight-etm3x.c index f0be12bd79e0..25f49b84a6d2 100644 --- a/drivers/coresight/coresight-etm3x.c +++ b/drivers/coresight/coresight-etm3x.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include "coresight-etm.h" @@ -1315,7 +1316,6 @@ static ssize_t seq_curr_state_show(struct device *dev, } pm_runtime_get_sync(drvdata->dev); - spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); @@ -1796,6 +1796,13 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); + drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ + if (!IS_ERR(drvdata->atclk)) { + ret = clk_prepare_enable(drvdata->atclk); + if (ret) + return ret; + } + drvdata->cpu = pdata ? pdata->cpu : 0; get_online_cpus(); @@ -1858,6 +1865,34 @@ static int etm_remove(struct amba_device *adev) return 0; } +#ifdef CONFIG_PM +static int etm_runtime_suspend(struct device *dev) +{ + struct amba_device *adev = to_amba_device(dev); + struct etm_drvdata *drvdata = amba_get_drvdata(adev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_disable_unprepare(drvdata->atclk); + + return 0; +} + +static int etm_runtime_resume(struct device *dev) +{ + struct amba_device *adev = to_amba_device(dev); + struct etm_drvdata *drvdata = amba_get_drvdata(adev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_prepare_enable(drvdata->atclk); + + return 0; +} +#endif + +static const struct dev_pm_ops etm_dev_pm_ops = { + SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL) +}; + static struct amba_id etm_ids[] = { { /* ETM 3.3 */ .id = 0x0003b921, @@ -1886,6 +1921,7 @@ static struct amba_driver etm_driver = { .drv = { .name = "coresight-etm3x", .owner = THIS_MODULE, + .pm = &etm_dev_pm_ops, }, .probe = etm_probe, .remove = etm_remove,