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client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD024.mail.protection.outlook.com (10.58.144.87) with Microsoft SMTP Server (TLS) id 15.1.160.8 via Frontend Transport; Thu, 30 Apr 2015 14:46:22 +0000 Received: from [az84smr01.freescale.net (B38339-11.am.freescale.net [10.81.92.140]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t3UEieiY026417; Thu, 30 Apr 2015 07:46:20 -0700 From: Shenwei Wang To: Subject: [PATCH 07/18] ARM: imx: Initialize the imx_timer structure Date: Thu, 30 Apr 2015 09:44:22 -0500 Message-ID: <1430405073-13106-8-git-send-email-shenwei.wang@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430405073-13106-1-git-send-email-shenwei.wang@freescale.com> References: <1430405073-13106-1-git-send-email-shenwei.wang@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(189002)(199003)(77096005)(47776003)(104016003)(77156002)(6806004)(2950100001)(5001960100002)(50226001)(62966003)(33646002)(87936001)(106466001)(50986999)(76176999)(48376002)(19580395003)(105606002)(85426001)(50466002)(36756003)(46102003)(2351001)(19580405001)(92566002)(229853001)(86362001)(110136002); DIR:OUT; SFP:1102; SCL:1; SRVR:BL2PR03MB451; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BL2PR03MB451; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:BL2PR03MB451; BCL:0; PCL:0; RULEID:; SRVR:BL2PR03MB451; X-Forefront-PRVS: 056297E276 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2015 14:46:22.1334 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2PR03MB451 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150430_074645_535242_3B3DF68E X-CRM114-Status: GOOD ( 10.34 ) X-Spam-Score: -0.2 (/) Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Initialized the imx_timer struct in the following two functions: mxc_timer_init mxc_timer_init_dt Signed-off-by: Shenwei Wang --- arch/arm/mach-imx/time.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 811d50a..451f761 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -31,6 +31,7 @@ #include #include #include +#include #include @@ -536,12 +537,29 @@ static void __init _mxc_timer_init(int irq, void __init mxc_timer_init(unsigned long pbase, int irq, int ver) { + struct imx_timer *timer; struct clk *clk_per = clk_get_sys("imx-gpt.0", "per"); struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); timer_base = ioremap(pbase, SZ_4K); BUG_ON(!timer_base); + timer = kzalloc(sizeof(struct imx_timer), GFP_KERNEL); + if (!timer) + panic("Can't allocate timer struct\n"); + + timer->timer_base = timer_base; + timer->version = ver; + timer->evt.name = "mxc_timer1"; + timer->evt.rating = 200; + timer->evt.features = CLOCK_EVT_FEAT_ONESHOT; + timer->evt.set_mode = mxc_set_mode; + timer->evt.set_next_event = v2_set_next_event; + timer->act.name = "i.MX Timer Tick"; + timer->act.flags = IRQF_TIMER | IRQF_IRQPOLL; + timer->act.dev_id = timer; + timer->act.handler = mxc_timer_interrupt; + _mxc_timer_init(irq, clk_per, clk_ipg); } @@ -565,11 +583,34 @@ static const struct imx_timer_ip_combo imx_timer_tables[] = { static void __init mxc_timer_init_dt(struct device_node *np) { struct clk *clk_per, *clk_ipg; - int irq; + int irq, i, ret, ver; + struct imx_timer *timer; if (timer_base) return; + for (i = 0; i < sizeof(imx_timer_tables) / + sizeof(struct imx_timer_ip_combo); i++) { + ret = of_device_is_compatible(np, imx_timer_tables[i].compat); + if (ret) { + ver = imx_timer_tables[i].version; + pr_err("<%s> compatible=%s timer_version=%d\r\n", + __func__, imx_timer_tables[i].compat, ver); + break; + } + } + + if (!ret) { + pr_err("<%s> timer device node is not supported\r\n", __func__); + return; + } + + timer = kzalloc(sizeof(struct imx_timer), GFP_KERNEL); + if (!timer) + panic("Can't allocate timer struct\n"); + + timer->timer_base = of_iomap(np, 0); + timer_base = of_iomap(np, 0); WARN_ON(!timer_base); irq = irq_of_parse_and_map(np, 0); @@ -581,8 +622,20 @@ static void __init mxc_timer_init_dt(struct device_node *np) if (IS_ERR(clk_per)) clk_per = of_clk_get_by_name(np, "per"); + timer->version = ver; + timer->evt.name = np->name; + timer->evt.rating = 200; + timer->evt.features = CLOCK_EVT_FEAT_ONESHOT; + timer->evt.set_mode = mxc_set_mode; + timer->evt.set_next_event = v2_set_next_event; + timer->act.name = np->name; + timer->act.flags = IRQF_TIMER | IRQF_IRQPOLL; + timer->act.dev_id = timer; + timer->act.handler = mxc_timer_interrupt; + _mxc_timer_init(irq, clk_per, clk_ipg); } + CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt); CLOCKSOURCE_OF_DECLARE(mx50_timer, "fsl,imx50-gpt", mxc_timer_init_dt);