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client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD052.mail.protection.outlook.com (10.58.53.67) with Microsoft SMTP Server (TLS) id 15.1.154.14 via Frontend Transport; Thu, 30 Apr 2015 14:46:29 +0000 Received: from [az84smr01.freescale.net (B38339-11.am.freescale.net [10.81.92.140]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t3UEieiZ026417; Thu, 30 Apr 2015 07:46:27 -0700 From: Shenwei Wang To: Subject: [PATCH 08/18] ARM: imx: Reimplemented the _mxc_timer_init based on IP version Date: Thu, 30 Apr 2015 09:44:23 -0500 Message-ID: <1430405073-13106-9-git-send-email-shenwei.wang@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430405073-13106-1-git-send-email-shenwei.wang@freescale.com> References: <1430405073-13106-1-git-send-email-shenwei.wang@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(339900001)(189002)(199003)(85426001)(87936001)(19580395003)(19580405001)(105606002)(106466001)(50466002)(86362001)(48376002)(50986999)(2351001)(33646002)(76176999)(229853001)(104016003)(77096005)(6806004)(50226001)(92566002)(2950100001)(46102003)(110136002)(5001960100002)(77156002)(62966003)(36756003)(47776003); DIR:OUT; SFP:1102; SCL:1; SRVR:BY1PR0301MB1190; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY1PR0301MB1190; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:BY1PR0301MB1190; BCL:0; PCL:0; RULEID:; SRVR:BY1PR0301MB1190; X-Forefront-PRVS: 056297E276 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2015 14:46:29.8647 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0301MB1190 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150430_074653_477281_8E0A232A X-CRM114-Status: GOOD ( 11.52 ) X-Spam-Score: -0.2 (/) Cc: linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reimplemented the function of _mxc_timer_init just based on the version of timer IP block. Signed-off-by: Shenwei Wang --- arch/arm/mach-imx/time.c | 75 +++++++++++++++++++++--------------------------- 1 file changed, 33 insertions(+), 42 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index 451f761..cf07401 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -486,53 +486,44 @@ static void __init _mxc_timer_init_v3(int irq, struct clk *clk_per, setup_irq(irq, &tm->act); } -static void __init _mxc_timer_init(int irq, - struct clk *clk_per, struct clk *clk_ipg) +static void __init _mxc_timer_init(int irq, struct clk *clk_per, + struct clk *clk_ipg, struct imx_timer *tm) { - uint32_t tctl_val; - - if (IS_ERR(clk_per)) { - pr_err("i.MX timer: unable to get clk\n"); - return; - } - if (!IS_ERR(clk_ipg)) - clk_prepare_enable(clk_ipg); - - clk_prepare_enable(clk_per); + switch (tm->version) { + case IMX_TIMER_V0: + tm->gpt_irq_enable = gpt_irq_enable_v0_v1; + tm->gpt_irq_disable = gpt_irq_disable_v0_v1; + tm->gpt_irq_acknowledge = gpt_irq_acknowledge_v0; + _mxc_timer_init_v0_v1(irq, clk_per, clk_ipg, tm); + break; - /* - * Initialise to a known state (all timers off, and timing reset) - */ + case IMX_TIMER_V1: + tm->gpt_irq_enable = gpt_irq_enable_v0_v1; + tm->gpt_irq_disable = gpt_irq_disable_v0_v1; + tm->gpt_irq_acknowledge = gpt_irq_acknowledge_v1; + _mxc_timer_init_v0_v1(irq, clk_per, clk_ipg, tm); + break; - __raw_writel(0, timer_base + MXC_TCTL); - __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - - if (timer_is_v2()) { - tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) { - tctl_val |= V2_TCTL_CLK_OSC_DIV8; - if (cpu_is_imx6dl() || cpu_is_imx6sx()) { - /* 24 / 8 = 3 MHz */ - __raw_writel(7 << V2_TPRER_PRE24M, - timer_base + MXC_TPRER); - tctl_val |= V2_TCTL_24MEN; - } - } else { - tctl_val |= V2_TCTL_CLK_PER; - } - } else { - tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; - } + case IMX_TIMER_V2: + tm->gpt_irq_enable = gpt_irq_enable_v2_v3; + tm->gpt_irq_disable = gpt_irq_disable_v2_v3; + tm->gpt_irq_acknowledge = gpt_irq_acknowledge_v2_v3; + _mxc_timer_init_v2(irq, clk_per, clk_ipg, tm); + break; - __raw_writel(tctl_val, timer_base + MXC_TCTL); + case IMX_TIMER_V3: + tm->gpt_irq_enable = gpt_irq_enable_v2_v3; + tm->gpt_irq_disable = gpt_irq_disable_v2_v3; + tm->gpt_irq_acknowledge = gpt_irq_acknowledge_v2_v3; + _mxc_timer_init_v3(irq, clk_per, clk_ipg, tm); + break; - /* init and register the timer to the framework */ - mxc_clocksource_init(clk_per, 0); - mxc_clockevent_init(clk_per, 0); + default: + pr_err("<%s> timer device node is not supported\r\n", __func__); + break; - /* Make irqs happen */ - setup_irq(irq, &mxc_timer_irq); + } } void __init mxc_timer_init(unsigned long pbase, int irq, int ver) @@ -560,7 +551,7 @@ void __init mxc_timer_init(unsigned long pbase, int irq, int ver) timer->act.dev_id = timer; timer->act.handler = mxc_timer_interrupt; - _mxc_timer_init(irq, clk_per, clk_ipg); + _mxc_timer_init(irq, clk_per, clk_ipg, timer); } struct imx_timer_ip_combo { @@ -633,7 +624,7 @@ static void __init mxc_timer_init_dt(struct device_node *np) timer->act.dev_id = timer; timer->act.handler = mxc_timer_interrupt; - _mxc_timer_init(irq, clk_per, clk_ipg); + _mxc_timer_init(irq, clk_per, clk_ipg, timer); } CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt);