From patchwork Wed May 13 16:34:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 6398931 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 577E0BEEE1 for ; Wed, 13 May 2015 16:58:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 530692034F for ; Wed, 13 May 2015 16:58:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 41FB52026F for ; Wed, 13 May 2015 16:58:15 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YsZtp-0003i9-6z; Wed, 13 May 2015 16:52:49 +0000 Received: from merlin.infradead.org ([2001:4978:20e::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YsZdI-0005PR-2F for linux-arm-kernel@bombadil.infradead.org; Wed, 13 May 2015 16:35:44 +0000 Received: from mail-pa0-f52.google.com ([209.85.220.52]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YsZdB-0006XC-GZ for linux-arm-kernel@lists.infradead.org; Wed, 13 May 2015 16:35:38 +0000 Received: by pabsx10 with SMTP id sx10so55619257pab.3 for ; Wed, 13 May 2015 09:35:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LyqfPPrZJUqbjYL3Iz/v1K1ZQ/vLD5Yn7pUHFrpDNa4=; b=WLAWKHWXvxiyjqcPIw0pszsxkZ4piklk51On877SSbw9GxCmJhBQgG3zBRsphIWCS2 7JRs5JRq7IOyIS4gyVMc0WbgPPBU0cfTiKxkaLwEOJ5PeiKA07HVy5tsfKFIBw9pvWaY Im79uEX7B/SVtH75w6ANgpffbqWcmvDfgjO4mpNLaQjfKAG/b4MM9WXgclgiFDYOnsC0 ds4k/xpQTUo5M9G50SK7+qdsgoLINaT4mQ+9Vrwe406epeLMPkKCztPAQg4k5w7u9D94 4rRBNXEcAICX/jxcMwtEr++wjLVWKpu3bmzR54tiSkPFPQu8R/bB9k4HWVZAOHBUBpbR nXaQ== X-Gm-Message-State: ALoCoQlcn2v6TH73VtPF1okBmrScj9MAeAQHwfb9rmmCkJ5VAfoE2McC9+lgK4Kq+2PUc6taSzSP X-Received: by 10.66.199.3 with SMTP id jg3mr38502931pac.127.1431534916186; Wed, 13 May 2015 09:35:16 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by mx.google.com with ESMTPSA id ue9sm19388667pbc.78.2015.05.13.09.35.14 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 13 May 2015 09:35:15 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH v4 12/13] coresight-etm4x: Read only access to the main management registers Date: Wed, 13 May 2015 10:34:20 -0600 Message-Id: <1431534861-24986-13-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431534861-24986-1-git-send-email-mathieu.poirier@linaro.org> References: <1431534861-24986-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150513_123537_644781_E8B74598 X-CRM114-Status: GOOD ( 12.01 ) X-Spam-Score: -2.6 (--) Cc: mathieu.poirier@linaro.org, linux-api@vger.kernel.org, linux-kernel@vger.kernel.org, zhang.chunyan@linaro.org, linux-arm-kernel@lists.infradead.org, kaixu.xia@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Having access to the ETMv4 management registers is very useful as they give meaningful information on how the IP block has been configured at synthesis time. Signed-off-by: Mathieu Poirier --- .../ABI/testing/sysfs-bus-coresight-devices-etm4x | 77 ++++++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.c | 53 ++++++++++++++- 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x index 648f28ded226..bde788dfd3f7 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x @@ -281,3 +281,80 @@ KernelVersion: 4.01 Contact: Mathieu Poirier Description: (RW) Mask for all 8 virtual machine ID comparator value registers (if implemented). + +What: /sys/bus/coresight/devices/.etm/mgmt/trcoslsr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the OS Lock Status Register (0x304). + The value it taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpdcr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Power Down Control Register + (0x310). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpdsr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Power Down Status Register + (0x314). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trclsr +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the SW Lock Status Register + (0xFB4). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcauthstatus +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Authentication Status Register + (0xFB8). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcdevid +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Device ID Register + (0xFC8). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcdevtype +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Device Type Register + (0xFCC). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr0 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Peripheral ID0 Register + (0xFE0). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr1 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Peripheral ID1 Register + (0xFE4). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr2 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Peripheral ID2 Register + (0xFE8). The value is taken directly from the HW. + +What: /sys/bus/coresight/devices/.etm/mgmt/trcpidr3 +Date: April 2015 +KernelVersion: 4.01 +Contact: Mathieu Poirier +Description: (R) Print the content of the Peripheral ID3 Register + (0xFEC). The value is taken directly from the HW. diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 02ee6fc97ddf..0568e4413411 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -2200,7 +2200,58 @@ static struct attribute *coresight_etmv4_attrs[] = { &dev_attr_cpu.attr, NULL, }; -ATTRIBUTE_GROUPS(coresight_etmv4); + +#define coresight_simple_func(name, offset) \ +static ssize_t name##_show(struct device *_dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct etmv4_drvdata *drvdata = dev_get_drvdata(_dev->parent); \ + return scnprintf(buf, PAGE_SIZE, "0x%x\n", \ + readl_relaxed(drvdata->base + offset)); \ +} \ +DEVICE_ATTR_RO(name) + +coresight_simple_func(trcoslsr, TRCOSLSR); +coresight_simple_func(trcpdcr, TRCPDCR); +coresight_simple_func(trcpdsr, TRCPDSR); +coresight_simple_func(trclsr, TRCLSR); +coresight_simple_func(trcauthstatus, TRCAUTHSTATUS); +coresight_simple_func(trcdevid, TRCDEVID); +coresight_simple_func(trcdevtype, TRCDEVTYPE); +coresight_simple_func(trcpidr0, TRCPIDR0); +coresight_simple_func(trcpidr1, TRCPIDR1); +coresight_simple_func(trcpidr2, TRCPIDR2); +coresight_simple_func(trcpidr3, TRCPIDR3); + +static struct attribute *coresight_etmv4_mgmt_attrs[] = { + &dev_attr_trcoslsr.attr, + &dev_attr_trcpdcr.attr, + &dev_attr_trcpdsr.attr, + &dev_attr_trclsr.attr, + &dev_attr_trcauthstatus.attr, + &dev_attr_trcdevid.attr, + &dev_attr_trcdevtype.attr, + &dev_attr_trcpidr0.attr, + &dev_attr_trcpidr1.attr, + &dev_attr_trcpidr2.attr, + &dev_attr_trcpidr3.attr, + NULL, +}; + +static const struct attribute_group coresight_etmv4_group = { + .attrs = coresight_etmv4_attrs, +}; + +static const struct attribute_group coresight_etmv4_mgmt_group = { + .attrs = coresight_etmv4_mgmt_attrs, + .name = "mgmt", +}; + +static const struct attribute_group *coresight_etmv4_groups[] = { + &coresight_etmv4_group, + &coresight_etmv4_mgmt_group, + NULL, +}; static void etm4_init_arch_data(void *info) {