From patchwork Fri May 15 08:11:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 6412521 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 46A4DC0432 for ; Fri, 15 May 2015 08:17:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5A159203F7 for ; Fri, 15 May 2015 08:17:05 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7F504203C0 for ; Fri, 15 May 2015 08:17:04 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtAl8-0006hg-Hp; Fri, 15 May 2015 08:14:18 +0000 Received: from mail.kernel.org ([198.145.29.136]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtAkE-0006H4-G9 for linux-arm-kernel@lists.infradead.org; Fri, 15 May 2015 08:13:23 +0000 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 23C1020456; Fri, 15 May 2015 08:13:05 +0000 (UTC) Received: from localhost.localdomain (unknown [104.207.83.1]) (using TLSv1.2 with cipher AES128-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B726820452; Fri, 15 May 2015 08:13:02 +0000 (UTC) From: shawnguo@kernel.org To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/9] ARM: imx: setup tctl register in device specific function Date: Fri, 15 May 2015 16:11:42 +0800 Message-Id: <1431677507-27420-5-git-send-email-shawnguo@kernel.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431677507-27420-1-git-send-email-shawnguo@kernel.org> References: <1431677507-27420-1-git-send-email-shawnguo@kernel.org> X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150515_011322_638258_DEF585A4 X-CRM114-Status: GOOD ( 16.72 ) X-Spam-Score: -0.0 (/) Cc: Shawn Guo , Daniel Lezcano , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Shawn Guo It creates device speicific function hook gpt_setup_tctl to set up gpt TCTL register. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 81 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 62 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index ed01813cfc76..c86e25922eb4 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -91,6 +91,7 @@ struct imx_timer { int irq; struct clk *clk_per; struct clk *clk_ipg; + void (*gpt_setup_tctl)(void); }; static struct imx_timer imxtm; @@ -306,9 +307,68 @@ static int __init mxc_clockevent_init(void) return 0; } +static void imx1_gpt_setup_tctl(void) +{ + u32 tctl_val; + + tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; + __raw_writel(tctl_val, imxtm.base + MXC_TCTL); +} +#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl + +static void imx31_gpt_setup_tctl(void) +{ + u32 tctl_val; + + tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (clk_get_rate(imxtm.clk_per) == V2_TIMER_RATE_OSC_DIV8) + tctl_val |= V2_TCTL_CLK_OSC_DIV8; + else + tctl_val |= V2_TCTL_CLK_PER; + + __raw_writel(tctl_val, imxtm.base + MXC_TCTL); +} + +static void imx6dl_gpt_setup_tctl(void) +{ + u32 tctl_val; + + tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; + if (clk_get_rate(imxtm.clk_per) == V2_TIMER_RATE_OSC_DIV8) { + tctl_val |= V2_TCTL_CLK_OSC_DIV8; + /* 24 / 8 = 3 MHz */ + __raw_writel(7 << V2_TPRER_PRE24M, imxtm.base + MXC_TPRER); + tctl_val |= V2_TCTL_24MEN; + } else { + tctl_val |= V2_TCTL_CLK_PER; + } + + __raw_writel(tctl_val, imxtm.base + MXC_TCTL); +} + +static void __init imx_timer_data_init(void) +{ + switch (imxtm.type) { + case GPT_TYPE_IMX1: + imxtm.gpt_setup_tctl = imx1_gpt_setup_tctl; + break; + case GPT_TYPE_IMX21: + imxtm.gpt_setup_tctl = imx21_gpt_setup_tctl; + break; + case GPT_TYPE_IMX31: + imxtm.gpt_setup_tctl = imx31_gpt_setup_tctl; + break; + case GPT_TYPE_IMX6DL: + imxtm.gpt_setup_tctl = imx6dl_gpt_setup_tctl; + break; + default: + BUG(); + } +} + static void __init _mxc_timer_init(void) { - uint32_t tctl_val; + imx_timer_data_init(); if (IS_ERR(imxtm.clk_per)) { pr_err("i.MX timer: unable to get clk\n"); @@ -327,24 +387,7 @@ static void __init _mxc_timer_init(void) __raw_writel(0, imxtm.base + MXC_TCTL); __raw_writel(0, imxtm.base + MXC_TPRER); /* see datasheet note */ - if (timer_is_v2()) { - tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; - if (clk_get_rate(imxtm.clk_per) == V2_TIMER_RATE_OSC_DIV8) { - tctl_val |= V2_TCTL_CLK_OSC_DIV8; - if (cpu_is_imx6dl() || cpu_is_imx6sx()) { - /* 24 / 8 = 3 MHz */ - __raw_writel(7 << V2_TPRER_PRE24M, - imxtm.base + MXC_TPRER); - tctl_val |= V2_TCTL_24MEN; - } - } else { - tctl_val |= V2_TCTL_CLK_PER; - } - } else { - tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; - } - - __raw_writel(tctl_val, imxtm.base + MXC_TCTL); + imxtm.gpt_setup_tctl(); /* init and register the timer to the framework */ mxc_clocksource_init();