From patchwork Sat May 16 07:58:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yingjoe Chen X-Patchwork-Id: 6419631 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7BB809F318 for ; Sat, 16 May 2015 08:04:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9F123203F7 for ; Sat, 16 May 2015 08:04:13 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B49C42057F for ; Sat, 16 May 2015 08:04:12 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtX2N-000380-8l; Sat, 16 May 2015 08:01:35 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YtX0a-0000t6-Gc; Sat, 16 May 2015 07:59:46 +0000 X-Listener-Flag: 11101 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 443897413; Sat, 16 May 2015 15:59:12 +0800 Received: from mtksdtcf02.mediatek.inc (10.21.12.142) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Sat, 16 May 2015 15:59:11 +0800 From: Yingjoe Chen To: Mark Rutland , Matthias Brugger , Thomas Gleixner , Russell King Subject: [PATCH v2 3/9] clocksource: mediatek: do not enable GPT_CLK_EVT when setup Date: Sat, 16 May 2015 15:58:24 +0800 Message-ID: <1431763110-443-4-git-send-email-yingjoe.chen@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1431763110-443-1-git-send-email-yingjoe.chen@mediatek.com> References: <1431763110-443-1-git-send-email-yingjoe.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150516_005944_814155_F0E9158A X-CRM114-Status: UNSURE ( 8.60 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.3 (+) Cc: devicetree@vger.kernel.org, Arnd Bergmann , Pawel Moll , Catalin Marinas , Daniel Lezcano , Stephen Boyd , linux-kernel@vger.kernel.org, Marc Carino , Rob Herring , linux-mediatek@lists.infradead.org, Sascha Hauer , Olof Johansson , Yingjoe Chen , srv_heupstream@mediatek.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Spurious mtk timer interrupt is noticed at boot and cause kernel crash. It seems if GPT is enabled, it will latch irq status even when its IRQ is disabled. When irq is enabled afterward, we see spurious interrupt. Change init flow to only enable GPT_CLK_SRC at mtk_timer_init. Signed-off-by: Yingjoe Chen --- drivers/clocksource/mtk_timer.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c index 68ab423..91206f9 100644 --- a/drivers/clocksource/mtk_timer.c +++ b/drivers/clocksource/mtk_timer.c @@ -157,8 +157,11 @@ static void mtk_timer_global_reset(struct mtk_clock_event_device *evt) } static void -mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) +mtk_timer_setup(struct mtk_clock_event_device *evt, + u8 timer, u8 option, u8 enable) { + u32 val; + writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE, evt->gpt_base + TIMER_CTRL_REG(timer)); @@ -167,8 +170,10 @@ mtk_timer_setup(struct mtk_clock_event_device *evt, u8 timer, u8 option) writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer)); - writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE, - evt->gpt_base + TIMER_CTRL_REG(timer)); + val = TIMER_CTRL_OP(option); + if (enable) + val |= TIMER_CTRL_ENABLE; + writel(val, evt->gpt_base + TIMER_CTRL_REG(timer)); } static void mtk_timer_enable_irq(struct mtk_clock_event_device *evt, u8 timer) @@ -235,12 +240,12 @@ static void __init mtk_timer_init(struct device_node *node) evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); /* Configure clock source */ - mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN); + mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN, 1); clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), node->name, rate, 300, 32, clocksource_mmio_readl_up); /* Configure clock event */ - mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT); + mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT, 0); clockevents_config_and_register(&evt->dev, rate, 0x3, 0xffffffff);