From patchwork Tue May 19 16:55:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 6439621 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D64899F318 for ; Tue, 19 May 2015 17:04:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E91C020454 for ; Tue, 19 May 2015 17:04:17 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3319A203B6 for ; Tue, 19 May 2015 17:04:16 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1YuktL-0003Hb-59; Tue, 19 May 2015 17:01:19 +0000 Received: from mail-pa0-f47.google.com ([209.85.220.47]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YukoP-0007Cb-BU for linux-arm-kernel@lists.infradead.org; Tue, 19 May 2015 16:56:17 +0000 Received: by pabru16 with SMTP id ru16so32196755pab.1 for ; Tue, 19 May 2015 09:55:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RKmEGgw+MqSaMyFcRDtDENO4Sv+poaM9IfYzGaPNK58=; b=l29hIGcjp72IrnEg/aJ7IjvbY28qxRUXep9oTnAp/G17WXJ1eb1TEhi4+43Gtzq81e ZgXBUUFNf3F3YYo0xKSYFqxjhETuq5aTjgUjh9TiGhgTE2HP0NzLtO9xr/v/xJ1fD/+z O2bFEv06XwfJLHkIcqqj7oQGRMoR4U3HNjoyvgpDC8N14q6cKrvTZDNBcAihUr7DKVRM Dm0GkHrWWM6GNQ4ynBARF5Q+1WF6qD0YwOr4PqwoLo5sJ2PzXrvy+QuXe/24j4hUuk61 loW+qrSPc31wZ8B85DfuF0i3ixBlTc5dm6liIwW3ZZiS1dOgJL5GBhxsFvJ8OmsbMf4d 71MA== X-Gm-Message-State: ALoCoQkZ4845t4191oBRujL6yGulYXj7JJqdvOJXiVamroSLnAIqJuQM/w20OatA27eZNHSTA8CD X-Received: by 10.68.142.42 with SMTP id rt10mr19704096pbb.27.1432054552411; Tue, 19 May 2015 09:55:52 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by mx.google.com with ESMTPSA id rx6sm11817453pbc.54.2015.05.19.09.55.51 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 May 2015 09:55:51 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 09/16] coresight: etm: retrieve and handle atclk Date: Tue, 19 May 2015 10:55:14 -0600 Message-Id: <1432054521-24807-10-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432054521-24807-1-git-send-email-mathieu.poirier@linaro.org> References: <1432054521-24807-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150519_095613_461334_411D2AFB X-CRM114-Status: GOOD ( 17.54 ) X-Spam-Score: -1.8 (-) Cc: mathieu.poirier@linaro.org, kaixu.xia@linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, zhang.chunyan@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Linus Walleij As can be seen from the datasheet of the CoreSight Components, DDI0401C A.1.1 the ETM has a clock signal apart from the AHB interconnect ("amba_pclk", that we're already handling) called ATCLK, ARM Trace Clock, that SoC implementers may provide from an entirely different clock source. So to model this correctly create an optional path for handling ATCLK alongside the PCLK so we don't break old platforms that only define PCLK ("amba_pclk") but still makes it possible for SoCs that have both clock signals (such as the DB8500) to fetch and prepare/enable/disable/ unprepare both clocks. The ATCLK is enabled and disabled using the runtime PM callbacks. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm.h | 2 ++ drivers/hwtracing/coresight/coresight-etm3x.c | 36 ++++++++++++++++++++++++++- 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h index d1421e1f8b8a..098ffbec0a44 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -140,6 +140,7 @@ * struct etm_drvdata - specifics associated to an ETM component * @base: memory mapped base address for this component. * @dev: the device entity associated to this component. + * @atclk: optional clock for the core parts of the ETM. * @csdev: component vitals needed by the framework. * @spinlock: only one at a time pls. * @cpu: the cpu this component is affined to. @@ -191,6 +192,7 @@ struct etm_drvdata { void __iomem *base; struct device *dev; + struct clk *atclk; struct coresight_device *csdev; spinlock_t spinlock; int cpu; diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c index 7f0df778bd85..018a00fda611 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x.c +++ b/drivers/hwtracing/coresight/coresight-etm3x.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include "coresight-etm.h" @@ -1315,7 +1316,6 @@ static ssize_t seq_curr_state_show(struct device *dev, } pm_runtime_get_sync(drvdata->dev); - spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); @@ -1796,6 +1796,13 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); + drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ + if (!IS_ERR(drvdata->atclk)) { + ret = clk_prepare_enable(drvdata->atclk); + if (ret) + return ret; + } + drvdata->cpu = pdata ? pdata->cpu : 0; get_online_cpus(); @@ -1858,6 +1865,32 @@ static int etm_remove(struct amba_device *adev) return 0; } +#ifdef CONFIG_PM +static int etm_runtime_suspend(struct device *dev) +{ + struct etm_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_disable_unprepare(drvdata->atclk); + + return 0; +} + +static int etm_runtime_resume(struct device *dev) +{ + struct etm_drvdata *drvdata = dev_get_drvdata(dev); + + if (drvdata && !IS_ERR(drvdata->atclk)) + clk_prepare_enable(drvdata->atclk); + + return 0; +} +#endif + +static const struct dev_pm_ops etm_dev_pm_ops = { + SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL) +}; + static struct amba_id etm_ids[] = { { /* ETM 3.3 */ .id = 0x0003b921, @@ -1886,6 +1919,7 @@ static struct amba_driver etm_driver = { .drv = { .name = "coresight-etm3x", .owner = THIS_MODULE, + .pm = &etm_dev_pm_ops, }, .probe = etm_probe, .remove = etm_remove,