From patchwork Tue May 19 16:55:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Poirier X-Patchwork-Id: 6439581 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 19505C0432 for ; Tue, 19 May 2015 17:01:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0F9D92047C for ; Tue, 19 May 2015 17:01:24 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3E4C920457 for ; Tue, 19 May 2015 17:01:22 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yukqp-0008Ur-Ho; Tue, 19 May 2015 16:58:43 +0000 Received: from mail-pd0-f176.google.com ([209.85.192.176]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1YukoM-00076q-FX for linux-arm-kernel@lists.infradead.org; Tue, 19 May 2015 16:56:13 +0000 Received: by pdbnk13 with SMTP id nk13so33040595pdb.1 for ; Tue, 19 May 2015 09:55:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Snw1O2QiSihGxibAhTtqwr5FAx3OynJtX6Y9RjJbdYw=; b=e3SIJJyc0czeBfK69lQEs/lid0WO4//R0rGvZVHNxUGdQtnI2Ol52UdcUQQ5/czfmQ mXdlxs0ayjuuymcQ6fe91pMgZBlNPK+gq+GOQKIt27UDFFEoydS+8ydexZiiGKywp/Lx 1VZ8+0cE7jB+zBKCakJmlO8Fzvg/WwHoI0i/UMXswf0A//3+QRKB3/rI/41Wgk2u8l1Q 2uyVGne8C+Aeot/YftQ6VA6LSKBDf8TeTdJKBj96Lxllf13m2cKnlYXD+4IbLhXcSuRW Ft2+JK2K8SSwJPlCXKs3wDqq4DWm+vqz1tibe7DuJKeg4fFdfCwz38Z5EnWLZ1SxpNWp pnSw== X-Gm-Message-State: ALoCoQnuldXD8YSw0fjMU0sY35VNijzxwLlFr9nt6drzCekVUSqPnL/XrJPvExfw2xI/4dPH1Zsi X-Received: by 10.66.192.74 with SMTP id he10mr55453170pac.145.1432054548452; Tue, 19 May 2015 09:55:48 -0700 (PDT) Received: from t430.cg.shawcable.net ([184.64.168.246]) by mx.google.com with ESMTPSA id rx6sm11817453pbc.54.2015.05.19.09.55.47 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 May 2015 09:55:47 -0700 (PDT) From: Mathieu Poirier To: gregkh@linuxfoundation.org Subject: [PATCH 06/16] coresight: etb: let runtime PM handle core clock Date: Tue, 19 May 2015 10:55:11 -0600 Message-Id: <1432054521-24807-7-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432054521-24807-1-git-send-email-mathieu.poirier@linaro.org> References: <1432054521-24807-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150519_095610_586526_FB6E1EC1 X-CRM114-Status: GOOD ( 17.13 ) X-Spam-Score: -1.8 (-) Cc: mathieu.poirier@linaro.org, kaixu.xia@linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, zhang.chunyan@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Linus Walleij This uses runtime PM to manage the PCLK ("amba_pclk") instead of screwing around with the framework by going in and taking a copy from the amba device. The amba bus core will unprepare and disable the clock when the device is unused when CONFIG_PM is selected, else the clock will be always on. Prior to this patch, as the AMBA primecell bus code enables the PCLK, it would be left on after probe as the clk_prepare_enable() and clk_disable_unprepare() was called and thus just increase and decreas the refcount by one, without it reaching zero and actually disabling the clock. Now the runtime PM callbacks will make sure the PCLK is properly disabled after probe. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etb10.c | 35 +++++++-------------------- 1 file changed, 9 insertions(+), 26 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 2a77d83130e6..df306aef4360 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include @@ -68,7 +68,6 @@ * @dev: the device entity associated to this component. * @csdev: component vitals needed by the framework. * @miscdev: specifics to handle "/dev/xyz.etb" entry. - * @clk: the clock this component is associated to. * @spinlock: only one at a time pls. * @in_use: synchronise user space access to etb buffer. * @buf: area of memory where ETB buffer content gets sent. @@ -81,7 +80,6 @@ struct etb_drvdata { struct device *dev; struct coresight_device *csdev; struct miscdevice miscdev; - struct clk *clk; spinlock_t spinlock; atomic_t in_use; u8 *buf; @@ -92,17 +90,14 @@ struct etb_drvdata { static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) { - int ret; u32 depth = 0; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; + pm_runtime_get_sync(drvdata->dev); /* RO registers don't need locking */ depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(drvdata->dev); return depth; } @@ -137,12 +132,9 @@ static void etb_enable_hw(struct etb_drvdata *drvdata) static int etb_enable(struct coresight_device *csdev) { struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - int ret; unsigned long flags; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; + pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); etb_enable_hw(drvdata); @@ -252,7 +244,7 @@ static void etb_disable(struct coresight_device *csdev) drvdata->enable = false; spin_unlock_irqrestore(&drvdata->spinlock, flags); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(drvdata->dev); dev_info(drvdata->dev, "ETB disabled\n"); } @@ -339,16 +331,12 @@ static const struct file_operations etb_fops = { static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) { - int ret; unsigned long flags; u32 etb_rdr, etb_sr, etb_rrp, etb_rwp; u32 etb_trg, etb_cr, etb_ffsr, etb_ffcr; struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); - ret = clk_prepare_enable(drvdata->clk); - if (ret) - goto out; - + pm_runtime_get_sync(drvdata->dev); spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->base); @@ -364,7 +352,7 @@ static ssize_t status_show(struct device *dev, CS_LOCK(drvdata->base); spin_unlock_irqrestore(&drvdata->spinlock, flags); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(drvdata->dev); return sprintf(buf, "Depth:\t\t0x%x\n" @@ -377,7 +365,7 @@ static ssize_t status_show(struct device *dev, "Flush ctrl:\t0x%x\n", etb_rdr, etb_sr, etb_rrp, etb_rwp, etb_trg, etb_cr, etb_ffsr, etb_ffcr); -out: + return -EINVAL; } static DEVICE_ATTR_RO(status); @@ -449,13 +437,8 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->spinlock); - drvdata->clk = adev->pclk; - ret = clk_prepare_enable(drvdata->clk); - if (ret) - return ret; - drvdata->buffer_depth = etb_get_buffer_depth(drvdata); - clk_disable_unprepare(drvdata->clk); + pm_runtime_put(&adev->dev); if (drvdata->buffer_depth & 0x80000000) return -EINVAL;