From patchwork Fri May 22 15:29:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 6465811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4504D9F46A for ; Fri, 22 May 2015 15:41:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 454AC200E8 for ; Fri, 22 May 2015 15:41:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3245D2049D for ; Fri, 22 May 2015 15:41:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yvp1J-0003JD-TM; Fri, 22 May 2015 15:37:57 +0000 Received: from mail-pd0-f169.google.com ([209.85.192.169]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Yvow5-0006c3-Ul for linux-arm-kernel@lists.infradead.org; Fri, 22 May 2015 15:32:35 +0000 Received: by pdbnk13 with SMTP id nk13so22208484pdb.1 for ; Fri, 22 May 2015 08:32:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P670WGZaH/WLrHWfuN1kVLxhFiqYClyVpI/6m/Z3Gpk=; b=ajWIs0ExlaRo5fgBTBxuDEPPM44awwQeJRQRgpPgrjvF7WInqk7IttpoFgxT0r/1E8 9kKLYLpaHOIjNe/X5s9B/7sAsqIlx2TLwAZ3x1Blh/Akvxyhbf1HF0vuF//1y7d2ZLOI UXD/H7jHWCvNz8kNlRDssHEX/w4k/NGMBvaeFeehBVo2LMDP7lqhoE1qSIcOJOUSHeGg UO2bAs8AYS8+YOH2oEkAFx9F56yw7fjXuJjzitdI0i7Sxm4v5+cA3f3DY0aTSnLYxz4c EzImJStXf5qiu8HWJeGunQ/Qxz8s+U/mflKeMUV3BusTUqlp34EANaC+dIgSbCXrTMbm 8ELA== X-Gm-Message-State: ALoCoQmI+g+fZQU/LidWsw9WhMV1mpejZdb1dIkfyjKSMoSa6At3GEQJOnGYIy95Akvw7uwiBLr4 X-Received: by 10.68.113.194 with SMTP id ja2mr16323684pbb.163.1432308730290; Fri, 22 May 2015 08:32:10 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id as1sm2474485pbc.39.2015.05.22.08.32.05 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 22 May 2015 08:32:09 -0700 (PDT) From: Shawn Guo To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 10/12] ARM: imx: provide gpt device specific irq functions Date: Fri, 22 May 2015 23:29:57 +0800 Message-Id: <1432308599-28643-11-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> References: <1432308599-28643-1-git-send-email-shawn.guo@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150522_083234_095035_390F67BD X-CRM114-Status: GOOD ( 14.30 ) X-Spam-Score: -1.8 (-) Cc: Shawn Guo , Daniel Lezcano , Arnd Bergmann , kernel@pengutronix.de, Shenwei Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP It splits irq enable/disable/acknowledge operations into device specific functions as the hooks in imx_gpt_data, so that we can save the use of timer_is_xxx() and cpu_is_xxx() checking in these irq functions. Signed-off-by: Shawn Guo --- arch/arm/mach-imx/time.c | 80 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 54 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c index a4f12c75050f..5fb8397d8fe2 100644 --- a/arch/arm/mach-imx/time.c +++ b/arch/arm/mach-imx/time.c @@ -100,6 +100,9 @@ struct imx_gpt_data { int reg_tcn; int reg_tcmp; void (*gpt_setup_tctl)(struct imx_timer *imxtm); + void (*gpt_irq_enable)(struct imx_timer *imxtm); + void (*gpt_irq_disable)(struct imx_timer *imxtm); + void (*gpt_irq_acknowledge)(struct imx_timer *imxtm); int (*set_next_event)(unsigned long evt, struct clock_event_device *ced); }; @@ -109,40 +112,53 @@ static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced) return container_of(ced, struct imx_timer, ced); } -static inline void gpt_irq_disable(struct imx_timer *imxtm) +static void imx1_gpt_irq_disable(struct imx_timer *imxtm) { unsigned int tmp; - if (timer_is_v2()) - writel_relaxed(0, imxtm->base + V2_IR); - else { - tmp = readl_relaxed(imxtm->base + MXC_TCTL); - writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); - } + tmp = readl_relaxed(imxtm->base + MXC_TCTL); + writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); } +#define imx21_gpt_irq_disable imx1_gpt_irq_disable -static inline void gpt_irq_enable(struct imx_timer *imxtm) +static void imx31_gpt_irq_disable(struct imx_timer *imxtm) { - if (timer_is_v2()) - writel_relaxed(1<<0, imxtm->base + V2_IR); - else { - writel_relaxed(readl_relaxed(imxtm->base + MXC_TCTL) | MX1_2_TCTL_IRQEN, - imxtm->base + MXC_TCTL); - } + writel_relaxed(0, imxtm->base + V2_IR); +} +#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable + +static void imx1_gpt_irq_enable(struct imx_timer *imxtm) +{ + unsigned int tmp; + + tmp = readl_relaxed(imxtm->base + MXC_TCTL); + writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL); +} +#define imx21_gpt_irq_enable imx1_gpt_irq_enable + +static void imx31_gpt_irq_enable(struct imx_timer *imxtm) +{ + writel_relaxed(1<<0, imxtm->base + V2_IR); +} +#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable + +static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm) +{ + writel_relaxed(0, imxtm->base + MX1_2_TSTAT); } -static void gpt_irq_acknowledge(struct imx_timer *imxtm) +static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm) { - if (timer_is_v1()) { - if (cpu_is_mx1()) - writel_relaxed(0, imxtm->base + MX1_2_TSTAT); - else - writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, + writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, imxtm->base + MX1_2_TSTAT); - } else if (timer_is_v2()) - writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); } +static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm) +{ + writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT); +} +#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge + static void __iomem *sched_clock_reg; static u64 notrace mxc_read_sched_clock(void) @@ -227,7 +243,7 @@ static void mxc_set_mode(enum clock_event_mode mode, local_irq_save(flags); /* Disable interrupt in GPT module */ - gpt_irq_disable(imxtm); + imxtm->gpt->gpt_irq_disable(imxtm); if (mode != imxtm->cem) { u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); @@ -235,7 +251,7 @@ static void mxc_set_mode(enum clock_event_mode mode, writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); /* Clear pending interrupt */ - gpt_irq_acknowledge(imxtm); + imxtm->gpt->gpt_irq_acknowledge(imxtm); } #ifdef DEBUG @@ -261,7 +277,7 @@ static void mxc_set_mode(enum clock_event_mode mode, * mode switching */ local_irq_save(flags); - gpt_irq_enable(imxtm); + imxtm->gpt->gpt_irq_enable(imxtm); local_irq_restore(flags); break; case CLOCK_EVT_MODE_SHUTDOWN: @@ -283,7 +299,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat); - gpt_irq_acknowledge(imxtm); + imxtm->gpt->gpt_irq_acknowledge(imxtm); ced->event_handler(ced); @@ -357,6 +373,9 @@ static const struct imx_gpt_data imx1_gpt_data = { .reg_tstat = MX1_2_TSTAT, .reg_tcn = MX1_2_TCN, .reg_tcmp = MX1_2_TCMP, + .gpt_irq_enable = imx1_gpt_irq_enable, + .gpt_irq_disable = imx1_gpt_irq_disable, + .gpt_irq_acknowledge = imx1_gpt_irq_acknowledge, .gpt_setup_tctl = imx1_gpt_setup_tctl, .set_next_event = mx1_2_set_next_event, }; @@ -365,6 +384,9 @@ static const struct imx_gpt_data imx21_gpt_data = { .reg_tstat = MX1_2_TSTAT, .reg_tcn = MX1_2_TCN, .reg_tcmp = MX1_2_TCMP, + .gpt_irq_enable = imx21_gpt_irq_enable, + .gpt_irq_disable = imx21_gpt_irq_disable, + .gpt_irq_acknowledge = imx21_gpt_irq_acknowledge, .gpt_setup_tctl = imx21_gpt_setup_tctl, .set_next_event = mx1_2_set_next_event, }; @@ -373,6 +395,9 @@ static const struct imx_gpt_data imx31_gpt_data = { .reg_tstat = V2_TSTAT, .reg_tcn = V2_TCN, .reg_tcmp = V2_TCMP, + .gpt_irq_enable = imx31_gpt_irq_enable, + .gpt_irq_disable = imx31_gpt_irq_disable, + .gpt_irq_acknowledge = imx31_gpt_irq_acknowledge, .gpt_setup_tctl = imx31_gpt_setup_tctl, .set_next_event = v2_set_next_event, }; @@ -381,6 +406,9 @@ static const struct imx_gpt_data imx6dl_gpt_data = { .reg_tstat = V2_TSTAT, .reg_tcn = V2_TCN, .reg_tcmp = V2_TCMP, + .gpt_irq_enable = imx6dl_gpt_irq_enable, + .gpt_irq_disable = imx6dl_gpt_irq_disable, + .gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge, .gpt_setup_tctl = imx6dl_gpt_setup_tctl, .set_next_event = v2_set_next_event, };