| Message ID | 1432915453-409-2-git-send-email-m-karicheri2@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 05/29/2015 12:04 PM, Murali Karicheri wrote: > All of the keystone devices have a separate register to hold post > divider value for main pll clock. Currently the fixed-postdiv > value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to > use a value of 2 for this. Now that we have fixed this in the pll > clock driver change the dt bindings for the same. > > Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> > --- > arch/arm/boot/dts/k2e-clocks.dtsi | 5 ++--- > arch/arm/boot/dts/k2hk-clocks.dtsi | 5 ++--- > arch/arm/boot/dts/k2l-clocks.dtsi | 5 ++--- > 3 files changed, 6 insertions(+), 9 deletions(-) > > diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi > index 4773d6a..d56d68f 100644 > --- a/arch/arm/boot/dts/k2e-clocks.dtsi > +++ b/arch/arm/boot/dts/k2e-clocks.dtsi > @@ -13,9 +13,8 @@ clocks { > #clock-cells = <0>; > compatible = "ti,keystone,main-pll-clock"; > clocks = <&refclksys>; > - reg = <0x02620350 4>, <0x02310110 4>; > - reg-names = "control", "multiplier"; > - fixed-postdiv = <2>; > + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; > + reg-names = "control", "multiplier", "post-divider"; > }; > > papllclk: papllclk@2620358 { > diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi > index d5adee3..af9b719 100644 > --- a/arch/arm/boot/dts/k2hk-clocks.dtsi > +++ b/arch/arm/boot/dts/k2hk-clocks.dtsi > @@ -22,9 +22,8 @@ clocks { > #clock-cells = <0>; > compatible = "ti,keystone,main-pll-clock"; > clocks = <&refclksys>; > - reg = <0x02620350 4>, <0x02310110 4>; > - reg-names = "control", "multiplier"; > - fixed-postdiv = <2>; > + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; > + reg-names = "control", "multiplier", "post-divider"; > }; > > papllclk: papllclk@2620358 { > diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi > index eb1e3e2..ef8464b 100644 > --- a/arch/arm/boot/dts/k2l-clocks.dtsi > +++ b/arch/arm/boot/dts/k2l-clocks.dtsi > @@ -22,9 +22,8 @@ clocks { > #clock-cells = <0>; > compatible = "ti,keystone,main-pll-clock"; > clocks = <&refclksys>; > - reg = <0x02620350 4>, <0x02310110 4>; > - reg-names = "control", "multiplier"; > - fixed-postdiv = <2>; > + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; > + reg-names = "control", "multiplier", "post-divider"; > }; > > papllclk: papllclk@2620358 { > Santosh, The clk driver update is already merged to v4.2-rc. Could you send this DT update as well for 4.2-rc? Murali
Olof, As discussed patch 1/2 is already made it via clock tree. Please pick the subject fix for your upcoming fixes pull request. On 5/29/2015 9:04 AM, Murali Karicheri wrote: > All of the keystone devices have a separate register to hold post > divider value for main pll clock. Currently the fixed-postdiv > value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to > use a value of 2 for this. Now that we have fixed this in the pll > clock driver change the dt bindings for the same. > > Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> > --- Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
On 7/31/2015 7:20 AM, Murali Karicheri wrote: > On 05/29/2015 12:04 PM, Murali Karicheri wrote: >> All of the keystone devices have a separate register to hold post >> divider value for main pll clock. Currently the fixed-postdiv >> value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to >> use a value of 2 for this. Now that we have fixed this in the pll >> clock driver change the dt bindings for the same. >> >> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> >> --- [..] > Santosh, > > The clk driver update is already merged to v4.2-rc. Could you send this > DT update as well for 4.2-rc? > Sure. Regards, Santosh
On Fri, Jul 31, 2015 at 08:30:03AM -0700, santosh shilimkar wrote: > Olof, > > As discussed patch 1/2 is already made it via clock tree. Please > pick the subject fix for your upcoming fixes pull request. > > On 5/29/2015 9:04 AM, Murali Karicheri wrote: > >All of the keystone devices have a separate register to hold post > >divider value for main pll clock. Currently the fixed-postdiv > >value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to > >use a value of 2 for this. Now that we have fixed this in the pll > >clock driver change the dt bindings for the same. > > > >Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> > >--- > Acked-by: Santosh Shilimkar <ssantosh@kernel.org> > > Thanks, applied. -Olof
On 7/31/15 1:30 PM, Olof Johansson wrote: > On Fri, Jul 31, 2015 at 08:30:03AM -0700, santosh shilimkar wrote: >> Olof, >> >> As discussed patch 1/2 is already made it via clock tree. Please >> pick the subject fix for your upcoming fixes pull request. >> >> On 5/29/2015 9:04 AM, Murali Karicheri wrote: >>> All of the keystone devices have a separate register to hold post >>> divider value for main pll clock. Currently the fixed-postdiv >>> value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to >>> use a value of 2 for this. Now that we have fixed this in the pll >>> clock driver change the dt bindings for the same. >>> >>> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> >>> --- >> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> >> >> > > Thanks, applied. > Thanks Olof !! Regards, Santosh
diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi index 4773d6a..d56d68f 100644 --- a/arch/arm/boot/dts/k2e-clocks.dtsi +++ b/arch/arm/boot/dts/k2e-clocks.dtsi @@ -13,9 +13,8 @@ clocks { #clock-cells = <0>; compatible = "ti,keystone,main-pll-clock"; clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>; - reg-names = "control", "multiplier"; - fixed-postdiv = <2>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; }; papllclk: papllclk@2620358 { diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi index d5adee3..af9b719 100644 --- a/arch/arm/boot/dts/k2hk-clocks.dtsi +++ b/arch/arm/boot/dts/k2hk-clocks.dtsi @@ -22,9 +22,8 @@ clocks { #clock-cells = <0>; compatible = "ti,keystone,main-pll-clock"; clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>; - reg-names = "control", "multiplier"; - fixed-postdiv = <2>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; }; papllclk: papllclk@2620358 { diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi index eb1e3e2..ef8464b 100644 --- a/arch/arm/boot/dts/k2l-clocks.dtsi +++ b/arch/arm/boot/dts/k2l-clocks.dtsi @@ -22,9 +22,8 @@ clocks { #clock-cells = <0>; compatible = "ti,keystone,main-pll-clock"; clocks = <&refclksys>; - reg = <0x02620350 4>, <0x02310110 4>; - reg-names = "control", "multiplier"; - fixed-postdiv = <2>; + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; + reg-names = "control", "multiplier", "post-divider"; }; papllclk: papllclk@2620358 {
All of the keystone devices have a separate register to hold post divider value for main pll clock. Currently the fixed-postdiv value used for k2hk/l/e SoCs works by sheer luck as u-boot happens to use a value of 2 for this. Now that we have fixed this in the pll clock driver change the dt bindings for the same. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> --- arch/arm/boot/dts/k2e-clocks.dtsi | 5 ++--- arch/arm/boot/dts/k2hk-clocks.dtsi | 5 ++--- arch/arm/boot/dts/k2l-clocks.dtsi | 5 ++--- 3 files changed, 6 insertions(+), 9 deletions(-)