From patchwork Fri Jun 5 17:49:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 6557081 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 854E1C0020 for ; Fri, 5 Jun 2015 18:00:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7F75220490 for ; Fri, 5 Jun 2015 18:00:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 75DBC204D8 for ; Fri, 5 Jun 2015 18:00:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z0vnP-0007jG-Gs; Fri, 05 Jun 2015 17:52:43 +0000 Received: from mail-wi0-f177.google.com ([209.85.212.177]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z0vnL-0006ua-VM for linux-arm-kernel@lists.infradead.org; Fri, 05 Jun 2015 17:52:41 +0000 Received: by wiga1 with SMTP id a1so28354497wig.0 for ; Fri, 05 Jun 2015 10:49:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=bYsBRcJJvFip/DUsrDPffdaGF5ap7PSqu4KFEFqasHo=; b=Me4e0Vh4kGojL4Rsm/Ylh3ct0Gn+1axbOzlNjGI1raz0P33MpeloYUiiri1knRhHqd dOMF4gDHokE9fvAOM0QyIeqLfZWYuMOM7lhK1DjjnFvsBMqknX6uVz6QIAJRLRdGkyMr VT7EGVPyyPx0OxsuoVmT8Zpmwnwzm0ADXczsxwPWCVQH+3EwKCsywx2Dh92cfZc+Zruh rxFu9/aaMvP7bcyKM0ozaAt62t6i76pkB/wZrsLIeal7oX8FIyl5zy/d4oPGsgnVcYuh OMI4r5qctlsn8hsAfVdReO9PxiDIPbiWi542sK0v2oXsgLF7RoRuaa+VzRjGOy4m5UZq FQAw== X-Received: by 10.180.105.38 with SMTP id gj6mr19906309wib.90.1433526573492; Fri, 05 Jun 2015 10:49:33 -0700 (PDT) Received: from rric.localhost (x5ce0c0b4.dyn.telefonica.de. [92.224.192.180]) by mx.google.com with ESMTPSA id a19sm4426281wiv.2.2015.06.05.10.49.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 05 Jun 2015 10:49:32 -0700 (PDT) From: Robert Richter To: Tejun Heo Subject: [PATCH v5 1/2] ahci: Add generic MSI-X support for single interrupts to SATA PCI driver Date: Fri, 5 Jun 2015 19:49:25 +0200 Message-Id: <1433526566-21136-2-git-send-email-rric@kernel.org> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1433526566-21136-1-git-send-email-rric@kernel.org> References: <1433526566-21136-1-git-send-email-rric@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150605_105240_211093_40D5804E X-CRM114-Status: GOOD ( 21.27 ) X-Spam-Score: -0.7 (/) Cc: linux-kernel@vger.kernel.org, Robert Richter , linux-ide@vger.kernel.org, Sunil Goutham , Jiang Liu , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Robert Richter This patch adds generic MSI-X support for single interrupts to the SATA PCI driver. MSI-X support is needed for host controller that only have MSI-X support implemented, but no MSI or intx. This patch only adds support for single interrupts, multiple per-port MSI-X interrupts are not yet implemented. The new implementation still initializes MSIs first. Only if that fails, the code tries to enable MSI-X. If that fails too, setup is continued with intx interrupts. To not break other chips by this generic code change, there are the following precautions: * Interrupt ranges are not enabled at all. * Only single interrupt mode is enabled for msix cap devices. Thus, only one interrupt will be setup. * During the discussion with Tejun we agreed to change the init sequence from msix-msi-intx to msi-msix-intx. Thus, if a device offers msi and init does not fail, the msix init code will not be executed. This is equivalent to current code. With this, the code only setups single mode msix as a last resort if msi fails. No interrupt range is enabled at all. Only one interrupt will be enabled. Changes of the patch series: v5: * updated patch subject that the patch only implements single IRQ * moved Cavium specific code to a separate patch * detect Cavium ThunderX device with PCI_CLASS_STORAGE_SATA_AHCI instead of vendor/dev id * added more comments to the code * enable single msix support for all kind of devices (removing strict check) * rebased onto update libata/for-4.2 with patch 1, 2 applied v4: * removed implementation of ahci_init_intx() * improved patch descriptions * rebased onto libata/for-4.2 v3: * store irq number in struct ahci_host_priv * change initialization order from msix-msi-intx to msi-msix-intx * improve comments in ahci_init_msix() * improve error message in ahci_init_msix() * do not enable MSI-X if MSI is actively disabled for the device v2: * determine irq vector from pci_dev->msi_list Based on a patch from Sunil Goutham . Signed-off-by: Robert Richter --- drivers/ata/ahci.c | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index a3c66c3bb76e..f300aa583678 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -1201,6 +1202,71 @@ static inline void ahci_gtf_filter_workaround(struct ata_host *host) {} #endif +static struct msi_desc *msix_get_desc(struct pci_dev *dev, u16 entry) +{ + struct msi_desc *desc; + + list_for_each_entry(desc, &dev->msi_list, list) { + if (desc->msi_attrib.entry_nr == entry) + return desc; + } + + return NULL; +} + +/* + * MSI-X support is needed for host controller that only have MSI-X + * support implemented, but no MSI or intx. For now, function + * ahci_init_msix() only implements single MSI-X support, but not + * multiple MSI-X per-port interrupts. + */ +static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports, + struct ahci_host_priv *hpriv) +{ + struct msi_desc *desc; + int rc, nvec; + struct msix_entry entry = {}; + + /* Do not init MSI-X if MSI is disabled for the device */ + if (hpriv->flags & AHCI_HFLAG_NO_MSI) + return -ENODEV; + + nvec = pci_msix_vec_count(pdev); + if (nvec < 0) + return nvec; + + if (!nvec) { + rc = -ENODEV; + goto fail; + } + + /* + * There can exist more than one vector (e.g. for error + * detection or hdd hotplug). Then the first vector is used, + * all others are ignored. Only enable the first entry here + * (entry.entry = 0). + */ + rc = pci_enable_msix_exact(pdev, &entry, 1); + if (rc < 0) + goto fail; + + desc = msix_get_desc(pdev, 0); /* first entry */ + if (!desc) { + rc = -EINVAL; + goto fail; + } + + hpriv->irq = desc->irq; + + return 1; +fail: + dev_err(&pdev->dev, + "failed to enable MSI-X with error %d, # of vectors: %d\n", + rc, nvec); + + return rc; +} + static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, struct ahci_host_priv *hpriv) { @@ -1260,6 +1326,17 @@ static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports, if (nvec >= 0) return nvec; + /* + * Only setup single mode MSI-X as a last resort if MSI fails: + * Initialize MSI-X after MSI and only if that fails, continue + * with intx interrupts on failure. Thus, MSI-X code is not + * executed if a device offers MSI and its initialization does + * not fail. + */ + nvec = ahci_init_msix(pdev, n_ports, hpriv); + if (nvec >= 0) + return nvec; + /* lagacy intx interrupts */ pci_intx(pdev, 1); hpriv->irq = pdev->irq;