From patchwork Fri Jun 5 17:49:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 6557171 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0676FC0020 for ; Fri, 5 Jun 2015 18:02:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3C018206FB for ; Fri, 5 Jun 2015 18:02:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5CB45206F5 for ; Fri, 5 Jun 2015 18:02:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z0vlg-00071H-B6; Fri, 05 Jun 2015 17:50:56 +0000 Received: from mail-wi0-f174.google.com ([209.85.212.174]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z0vlR-0006ub-Mz for linux-arm-kernel@lists.infradead.org; Fri, 05 Jun 2015 17:50:42 +0000 Received: by wifx6 with SMTP id x6so28144040wif.0 for ; Fri, 05 Jun 2015 10:49:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=jZCBGFJxC/2M4oy0I1IwFn4R4V4Y5SmqDYYBlf3XtjQ=; b=KM3Fj3jxpvYjrD1Ez0hFklm3PW3sJHuE0LMTDcm/yn2i0UCBzxa+RgiJ/gGZSOi49I R1K3wlIyQ1jYLWWY94k/8Q2LG/Fp8LZ3iHbMYcGRIvchnsuOsqO0dYxJnwRMXMyyH1Yw P5x96nF/oKWjo65LHkM7ec5vAc11DlZt66wrIYpKBSI8lgeEGs2zMnQjh9LSpb5aHSP+ HFJrHjFaY/7TBEfr4STBwfnSjEhx1ZLfqMMp9HcyPEKz8THJw9fKRqAMCm0yw8k4lbkf 8iqU2Yd6npxW1U6sVi+tdgIolpdtTOvfaKHrAi6HO3nJLpb0oVD+BWpO5goaURNM7uin vBTQ== X-Received: by 10.194.23.197 with SMTP id o5mr8542654wjf.75.1433526574707; Fri, 05 Jun 2015 10:49:34 -0700 (PDT) Received: from rric.localhost (x5ce0c0b4.dyn.telefonica.de. [92.224.192.180]) by mx.google.com with ESMTPSA id a19sm4426281wiv.2.2015.06.05.10.49.33 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 05 Jun 2015 10:49:34 -0700 (PDT) From: Robert Richter To: Tejun Heo Subject: [PATCH v5 2/2] ahci: Add support for Cavium's ThunderX host controller Date: Fri, 5 Jun 2015 19:49:26 +0200 Message-Id: <1433526566-21136-3-git-send-email-rric@kernel.org> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1433526566-21136-1-git-send-email-rric@kernel.org> References: <1433526566-21136-1-git-send-email-rric@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150605_105041_936247_E2D40235 X-CRM114-Status: GOOD ( 12.14 ) X-Spam-Score: -0.7 (/) Cc: linux-kernel@vger.kernel.org, Robert Richter , linux-ide@vger.kernel.org, Sunil Goutham , Jiang Liu , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Robert Richter This patch adds support for Cavium's ThunderX host controller. The controller resides on the SoC and is a AHCI compatible SATA controller with one port, compliant with Serial ATA 3.1 and AHCI Revision 1.31. There can exists multiple SATA controllers on the SoC. The controller depends on MSI-X support since the PCI ECAM controller on the SoC does not implement MSI nor lagacy intx interrupt support. Thus, during device initialization, if MSI fails MSI-X will be used to enable the device's interrupts. The controller uses non-standard BAR0 for its register range. The already existing device lookup (vendor and device id) that is already implemented for other host controllers is used to change the PCI BAR. Signed-off-by: Robert Richter --- drivers/ata/ahci.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index f300aa583678..094649db3330 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -53,6 +53,7 @@ enum { AHCI_PCI_BAR_STA2X11 = 0, + AHCI_PCI_BAR_CAVIUM = 0, AHCI_PCI_BAR_ENMOTUS = 2, AHCI_PCI_BAR_STANDARD = 5, }; @@ -1379,11 +1380,13 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) dev_info(&pdev->dev, "PDC42819 can only drive SATA devices with this driver\n"); - /* Both Connext and Enmotus devices use non-standard BARs */ + /* Some devices use non-standard BARs */ if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) ahci_pci_bar = AHCI_PCI_BAR_STA2X11; else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; + else if (pdev->vendor == 0x177d && pdev->device == 0xa01c) + ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; /* * The JMicron chip 361/363 contains one SATA controller and one