From patchwork Sat Jun 6 03:57:27 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Ulli Kroll X-Patchwork-Id: 6558851 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 81C589F46A for ; Sat, 6 Jun 2015 04:01:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 81350207B4 for ; Sat, 6 Jun 2015 04:01:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7A3C6207B8 for ; Sat, 6 Jun 2015 04:01:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z15GA-0001Gh-E3; Sat, 06 Jun 2015 03:59:02 +0000 Received: from mail-wg0-x233.google.com ([2a00:1450:400c:c00::233]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z15Fb-00014G-Lv for linux-arm-kernel@lists.infradead.org; Sat, 06 Jun 2015 03:58:28 +0000 Received: by wgme6 with SMTP id e6so68773598wgm.2 for ; Fri, 05 Jun 2015 20:58:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=J0ocXaKQXJ8UK2g7kq2Cn2HzrBpafpKcvTvSFcBcn0Y=; b=q0d4E0lh6zKKkR/L9nB5/bGNuNYD7aMtjHCpVh2/FH+iRcEiHV4Ydkod7QTmIStJxn JQ4mrdw2wlhCxd8NisH3lpld3Ne2E8y+Wa5Rjk5LQAjqpZwHj4q4Q7q70l7QtHEDN1gt gqUvLyWGP7pClO+8X6+UBnVMG1WG39JrcCPpcWxk+a7rWMMah8DsillTb75DE1e1/+ZT ybH/EkTTyZ0qKOmoDGcv6bKQe9Rc6c9jPokenjV1wIbEKWMm1Lnn0Va/lX1sQPzArrfW GcuNcrZZctcny67vbHDo0QyQPhMQVGY+G0Xx02FGPKEerdpTmJxe4h6bnSPyBgW4yR0t MKaA== X-Received: by 10.180.188.109 with SMTP id fz13mr2384813wic.74.1433563090765; Fri, 05 Jun 2015 20:58:10 -0700 (PDT) Received: from localhost ([89.204.135.80]) by mx.google.com with ESMTPSA id v3sm607676wix.8.2015.06.05.20.58.03 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 05 Jun 2015 20:58:10 -0700 (PDT) From: Hans Ulli Kroll To: linux-kernel@vger.kernel.org Subject: [PATCH 5/6] ARM:Gemini:use timer 1 as clockevent timer Date: Sat, 6 Jun 2015 05:57:27 +0200 Message-Id: <1433563048-21922-6-git-send-email-ulli.kroll@googlemail.com> X-Mailer: git-send-email 2.4.2 In-Reply-To: <1433563048-21922-1-git-send-email-ulli.kroll@googlemail.com> References: <1433563048-21922-1-git-send-email-ulli.kroll@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150605_205827_865195_881942B2 X-CRM114-Status: GOOD ( 17.64 ) X-Spam-Score: -0.8 (/) Cc: Hans Ulli Kroll , linux-arm-kernel@lists.infradead.org, Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch is based on openwrt patch found in target/linux/gemini/patches-3.18/160-gemini-timers.patch It removes usage of timer 2 as clockevent timer and uses timer 1. Also setup the needed register for interrupt handling missed in the initial patch Signed-off-by: Hans Ulli Kroll --- arch/arm/mach-gemini/time.c | 106 ++++++++++++++++++++++++++------------------ 1 file changed, 62 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c index e919b96..29ec2c3 100644 --- a/arch/arm/mach-gemini/time.c +++ b/arch/arm/mach-gemini/time.c @@ -63,19 +63,11 @@ static int gemini_timer_set_next_event(unsigned long cycles, { u32 cr; - cr = readl(TIMER_CR); - - /* This may be overdoing it, feel free to test without this */ - cr &= ~TIMER_2_CR_ENABLE; - cr &= ~TIMER_2_CR_INT; - writel(cr, TIMER_CR); - - /* Set next event */ - writel(cycles, TIMER_COUNT(GEMINI_TIMER2_BASE)); - writel(cycles, TIMER_LOAD(GEMINI_TIMER2_BASE)); - cr |= TIMER_2_CR_ENABLE; - cr |= TIMER_2_CR_INT; - writel(cr, TIMER_CR); + /* Setup the match register */ + cr = readl(TIMER_COUNT(GEMINI_TIMER1_BASE)); + writel(cr + cycles, TIMER_MATCH1(GEMINI_TIMER1_BASE)); + if (readl(TIMER_COUNT(GEMINI_TIMER1_BASE)) - cr > cycles) + return -ETIME; return 0; } @@ -87,32 +79,55 @@ static void gemini_timer_set_mode(enum clock_event_mode mode, u32 cr; switch (mode) { - case CLOCK_EVT_MODE_PERIODIC: - /* Start the timer */ - writel(period, - TIMER_COUNT(GEMINI_TIMER2_BASE)); - writel(period, - TIMER_LOAD(GEMINI_TIMER2_BASE)); + case CLOCK_EVT_MODE_PERIODIC: + /* Stop timer and interrupt. */ + cr = readl(TIMER_CR); + cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); + writel(cr, TIMER_CR); + + /* Setup timer to fire at 1/HZ intervals. */ + cr = 0xffffffff - (period - 1); + writel(cr, TIMER_COUNT(GEMINI_TIMER1_BASE)); + writel(cr, TIMER_LOAD(GEMINI_TIMER1_BASE)); + + /* enable interrupt on overflaw */ + cr = readl(TIMER_INTR_MASK); + cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2); + cr |= TIMER_1_INT_OVERFLOW; + writel(cr, TIMER_INTR_MASK); + + /* start the timer */ cr = readl(TIMER_CR); - cr |= TIMER_2_CR_ENABLE; - cr |= TIMER_2_CR_INT; + cr |= TIMER_1_CR_ENABLE | TIMER_1_CR_INT; writel(cr, TIMER_CR); break; + case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_UNUSED: - case CLOCK_EVT_MODE_SHUTDOWN: - case CLOCK_EVT_MODE_RESUME: - /* - * Disable also for oneshot: the set_next() call will - * arm the timer instead. - */ + case CLOCK_EVT_MODE_SHUTDOWN: + /* Stop timer and interrupt. */ + cr = readl(TIMER_CR); + cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT); + writel(cr, TIMER_CR); + + /* Setup counter start from 0 */ + writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE)); + writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE)); + + /* enable interrupt */ + cr = readl(TIMER_INTR_MASK); + cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2); + cr |= TIMER_1_INT_MATCH1; + writel(cr, TIMER_INTR_MASK); + + /* start the timer */ cr = readl(TIMER_CR); - cr &= ~TIMER_2_CR_ENABLE; - cr &= ~TIMER_2_CR_INT; + cr |= TIMER_1_CR_ENABLE; writel(cr, TIMER_CR); break; - default: - break; + + case CLOCK_EVT_MODE_RESUME: + break; } } @@ -120,6 +135,7 @@ static void gemini_timer_set_mode(enum clock_event_mode mode, static struct clock_event_device gemini_clockevent = { .name = "TIMER2", .rating = 300, /* Reasonably fast and accurate clock event */ + .shift = 32, .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, .set_next_event = gemini_timer_set_next_event, .set_mode = gemini_timer_set_mode, @@ -172,20 +188,22 @@ void __init gemini_timer_init(void) } /* - * Make irqs happen for the system timer + * Reset the interrupt mask and status + */ + writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK); + writel(0, TIMER_INTR_STATE); + writel(TIMER_1_CR_UPDOWN | TIMER_3_CR_ENABLE | TIMER_3_CR_UPDOWN, + TIMER_CR); + + /* + * Setup clockevent timer (interrupt-driven.) */ - setup_irq(IRQ_TIMER2, &gemini_timer_irq); - - /* Enable and use TIMER1 as clock source */ - writel(0xffffffff, TIMER_COUNT(GEMINI_TIMER1_BASE)); - writel(0xffffffff, TIMER_LOAD(GEMINI_TIMER1_BASE)); - writel(TIMER_1_CR_ENABLE, TIMER_CR); - if (clocksource_mmio_init(TIMER_COUNT(GEMINI_TIMER1_BASE), - "TIMER1", tick_rate, 300, 32, - clocksource_mmio_readl_up)) - pr_err("timer: failed to initialize gemini clock source\n"); - - /* Configure and register the clockevent */ + writel(0, TIMER_COUNT(GEMINI_TIMER1_BASE)); + writel(0, TIMER_LOAD(GEMINI_TIMER1_BASE)); + writel(0, TIMER_MATCH1(GEMINI_TIMER1_BASE)); + writel(0, TIMER_MATCH2(GEMINI_TIMER1_BASE)); + setup_irq(IRQ_TIMER1, &gemini_timer_irq); + gemini_clockevent.cpumask = cpumask_of(0); clockevents_config_and_register(&gemini_clockevent, tick_rate, 1, 0xffffffff); }