From patchwork Mon Jun 8 07:11:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 6563191 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2B550C0020 for ; Mon, 8 Jun 2015 07:14:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 236C120544 for ; Mon, 8 Jun 2015 07:14:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C88B20511 for ; Mon, 8 Jun 2015 07:14:52 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z1rEg-0008DB-ML; Mon, 08 Jun 2015 07:12:42 +0000 Received: from mail-pd0-f170.google.com ([209.85.192.170]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z1rEZ-000884-Na; Mon, 08 Jun 2015 07:12:36 +0000 Received: by pdbnf5 with SMTP id nf5so97490248pdb.2; Mon, 08 Jun 2015 00:12:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t4uThA7mvEaSbNgRbNjykwuP4BlR9B5l8uHAdNopAuQ=; b=CnxZQRpHTECJFtDijoW7A8JTw+pFIiDXoMwGHO48N9us4li9V4p1N3HU/4HbXw3nXy BFlob1kikYpxrTzjN41hm5fBdeaHkKClDwkT4Pvm5t5ImLhFV5V0DapXzhyNMvPMo8dB RbjXgda5VdbHEuU1fwysIbiSwF1FaZUvWJKogpaLlWuVDTrd5wy5bkE+lE+e5KBw7DPe CjNCo3vLmXVzz2P+m6Fz9WabEZW/yrp2zEjQz/gRWJygeZz06TEtWGV2qTTuBGzBbrYt TbvLA4gV/tbFQiZHaz50AD+rB5vLtCxIQWzycg4RIPPm9u+l0gw2tdCu6Wk1DzCPN/dk /eSw== X-Received: by 10.68.245.67 with SMTP id xm3mr26831227pbc.45.1433747534654; Mon, 08 Jun 2015 00:12:14 -0700 (PDT) Received: from localhost.localdomain ([192.253.240.41]) by mx.google.com with ESMTPSA id nt15sm1495125pdb.14.2015.06.08.00.12.07 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 08 Jun 2015 00:12:13 -0700 (PDT) From: Caesar Wang To: Heiko Stuebner Subject: [PATCH v5 1/3] ARM: rockchip: fix the CPU soft reset Date: Mon, 8 Jun 2015 15:11:34 +0800 Message-Id: <1433747496-7642-2-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433747496-7642-1-git-send-email-wxt@rock-chips.com> References: <1433747496-7642-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150608_001235_854263_D0119367 X-CRM114-Status: GOOD ( 14.79 ) X-Spam-Score: -1.8 (-) Cc: Russell King , Dmitry Torokhov , dianders@chromium.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Caesar Wang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We need different orderings when turning a core on and turning a core off. In one case we need to assert reset before turning power off. In ther other case we need to turn power on and the deassert reset. In general, the correct flow is: CPU off: reset_control_assert regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd)) wait_for_power_domain_to_turn_off CPU on: regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0) wait_for_power_domain_to_turn_on reset_control_deassert This is needed for stressing CPU up/down, as per: cd /sys/devices/system/cpu/ for i in $(seq 10000); do echo "================= $i ============" for j in $(seq 100); do while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "000"" ]] echo 0 > cpu1/online echo 0 > cpu2/online echo 0 > cpu3/online done while [[ "$(cat cpu1/online)$(cat cpu2/online)$(cat cpu3/online)" != "111" ]]; do echo 1 > cpu1/online echo 1 > cpu2/online echo 1 > cpu3/online done done done The following is reproducile log: [34466.186812] PM: noirq suspend of devices complete after 0.669 msecs [34466.186824] Disabling non-boot CPUs ... [34466.187509] CPU1: shutdown [34466.188672] CPU2: shutdown [34473.736627] Kernel panic - not syncing:Watchdog detected hard LOCKUP on cpu 0 ....... or others similar log: ....... [ 4072.454453] CPU1: shutdown [ 4072.504436] CPU2: shutdown [ 4072.554426] CPU3: shutdown [ 4072.577827] CPU1: Booted secondary processor [ 4072.582611] CPU2: Booted secondary processor [ 4072.587426] CPU3: Booted secondary processor Signed-off-by: Caesar Wang Reviewed-by: Doug Anderson Changes in v5: - back to v2 cpu on/off flow, As Heiko point out in patch v3. - delay more time in rockchip_boot_secondary(). From CPU up/down tests, Needed more time to complete CPU process. In order to ensure a more, Here that be delayed 1ms. Changes in v4: - Add reset_control_put(rstc) for the non-error case. Changes in v3: - FIx the PATCH v2, it doesn't work on chromium 3.14. Changes in v2: - As Heiko suggestion, re-adjust the cpu on/off flow. CPU off: reset_control_assert regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), BIT(pd)) wait_for_power_domain_to_turn_off CPU on: regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), 0) wait_for_power_domain_to_turn_on reset_control_deassert --- arch/arm/mach-rockchip/platsmp.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index 5b4ca3c..bd40852 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -72,6 +72,7 @@ static struct reset_control *rockchip_get_core_reset(int cpu) static int pmu_set_power_domain(int pd, bool on) { u32 val = (on) ? 0 : BIT(pd); + struct reset_control *rstc = rockchip_get_core_reset(pd); int ret; /* @@ -80,20 +81,15 @@ static int pmu_set_power_domain(int pd, bool on) * processor is powered down. */ if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { - struct reset_control *rstc = rockchip_get_core_reset(pd); - + /* We only require the reset on the RK3288 at the moment */ if (IS_ERR(rstc)) { pr_err("%s: could not get reset control for core %d\n", __func__, pd); return PTR_ERR(rstc); } - if (on) - reset_control_deassert(rstc); - else + if (!on) reset_control_assert(rstc); - - reset_control_put(rstc); } ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val); @@ -112,6 +108,12 @@ static int pmu_set_power_domain(int pd, bool on) } } + if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9 && on) + reset_control_deassert(rstc); + + if (!IS_ERR(rstc)) + reset_control_put(rstc); + return 0; } @@ -148,7 +150,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, * sram_base_addr + 4: 0xdeadbeaf * sram_base_addr + 8: start address for pc * */ - udelay(10); + mdelay(1); writel(virt_to_phys(rockchip_secondary_startup), sram_base_addr + 8); writel(0xDEADBEAF, sram_base_addr + 4);