| Message ID | 1433868446-11028-4-git-send-email-thomas.petazzoni@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jun 09, 2015 at 06:46:55PM +0200, Thomas Petazzoni wrote: > After updating to a more recent version of the Armada 375, we realized > that some of the pins documented as having a NAND-related > functionality in fact did not have such functionality. This commit > updates the pinctrl driver accordingly. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > Cc: <stable@vger.kernel.org> # v3.15+ > Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") > --- > .../devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 4 ++-- > drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 -- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt > index 7de0cda..bedbe42 100644 > --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt > @@ -22,8 +22,8 @@ mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) > mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) > mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) > mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) > -mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck) > -mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1) > +mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) > +mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) From armada-375.dtsi: nand_pins: nand-pins { marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp11", "mpp12", "mpp13"; marvell,function = "nand"; }; Don't you also need to remove mpp9 and mpp10 from here? What does pinctrl do when you ask for pins which are not a member of the function? Andrew
On Tue, Jun 9, 2015 at 6:46 PM, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> wrote: > After updating to a more recent version of the Armada 375, we realized > that some of the pins documented as having a NAND-related > functionality in fact did not have such functionality. This commit > updates the pinctrl driver accordingly. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > Cc: <stable@vger.kernel.org> # v3.15+ > Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") Patch applied. Yours, Linus Walleij
Dear Andrew Lunn, On Tue, 9 Jun 2015 18:58:43 +0200, Andrew Lunn wrote: > From armada-375.dtsi: > > nand_pins: nand-pins { > marvell,pins = "mpp0", "mpp1", "mpp2", > "mpp3", "mpp4", "mpp5", > "mpp6", "mpp7", "mpp8", > "mpp9", "mpp10", "mpp11", > "mpp12", "mpp13"; > marvell,function = "nand"; > }; > > Don't you also need to remove mpp9 and mpp10 from here? What does > pinctrl do when you ask for pins which are not a member of the > function? In fact, no. Look at the patch: MPP_MODE(9, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "nf", "wen"), MPP_FUNCTION(0x2, "spi0", "sck"), MPP_FUNCTION(0x3, "spi1", "sck"), MPP_FUNCTION(0x5, "nand", "we")), MPP_MODE(10, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "nf", "ren"), MPP_FUNCTION(0x2, "dram", "vttctrl"), MPP_FUNCTION(0x3, "led", "c1"), MPP_FUNCTION(0x5, "nand", "re"), See how both pins had a "nf" function (0x1) and a "nand" function (0x5). I didn't even notice that when doing the patch, so my commit log was slightly confusing. The "nf" functions were incorrect. The "nand" functions were correct, and already used by armada-375.dtsi. I have just tested NAND on Armada 375 DB with all the pinctrl patches applied, and it works fine (created a UBI device, with a volume, etc.). Best regards, Thomas
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt index 7de0cda..bedbe42 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -22,8 +22,8 @@ mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) -mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck) -mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1) +mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) +mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) mpp11 11 gpio, dev(a0), led(c2), audio(sdo) mpp12 12 gpio, dev(a1), audio(bclk) mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c index ca1e757..e740a42 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c @@ -98,13 +98,11 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { MPP_FUNCTION(0x5, "nand", "ce")), MPP_MODE(9, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "nf", "wen"), MPP_FUNCTION(0x2, "spi0", "sck"), MPP_FUNCTION(0x3, "spi1", "sck"), MPP_FUNCTION(0x5, "nand", "we")), MPP_MODE(10, MPP_FUNCTION(0x0, "gpio", NULL), - MPP_FUNCTION(0x1, "nf", "ren"), MPP_FUNCTION(0x2, "dram", "vttctrl"), MPP_FUNCTION(0x3, "led", "c1"), MPP_FUNCTION(0x5, "nand", "re"),
After updating to a more recent version of the Armada 375, we realized that some of the pins documented as having a NAND-related functionality in fact did not have such functionality. This commit updates the pinctrl driver accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: <stable@vger.kernel.org> # v3.15+ Fixes: ce3ed59dcddd ("pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375") --- .../devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt | 4 ++-- drivers/pinctrl/mvebu/pinctrl-armada-375.c | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-)