From patchwork Wed Jun 10 20:09:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Thompson X-Patchwork-Id: 6584521 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7B5FFC0020 for ; Wed, 10 Jun 2015 20:13:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9276C2060D for ; Wed, 10 Jun 2015 20:13:28 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AB517205F9 for ; Wed, 10 Jun 2015 20:13:27 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z2mKf-0004KJ-5k; Wed, 10 Jun 2015 20:10:41 +0000 Received: from mail-wi0-f181.google.com ([209.85.212.181]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z2mKJ-00034O-Ot for linux-arm-kernel@lists.infradead.org; Wed, 10 Jun 2015 20:10:21 +0000 Received: by wibdq8 with SMTP id dq8so57811375wib.1 for ; Wed, 10 Jun 2015 13:09:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KoQAwskMIuM5AB4cteE1FZO8NTlz2wUBndYNxt6iPBs=; b=IiDInN2PZSZXp+BNgn5QJsL6MMWB/owB2OpmExbt0MI+XVEvhYWlyrCLRHOOyxNb7F E+LQYuyA1jMSY0GU4cQY7mKMNeKBhR6ilsU0C3nK+gllo991KIJPg8onBRL89Emr05EL wcc4sZWVi+RfqRchJKHKkruaFw9eEGKBoN5y46d92Z6058SIuX9Je9hUYkKZL6jkJK+d EL7FN1Sx/aVHPUSMaGsF8aXuywYm39L6gTlmzKjVLVcC1iBV7TlQpYt0dx7WF5y9w0l4 F26NLmGxzSVP92J9awjN3Vvn7hQ8A7Z/FUUmk3ApvnYipV5RXl6p557h7EF6NGdF5Dtu sC7Q== X-Gm-Message-State: ALoCoQkjIGcVjuY9GzHFni8aedH1cNG7TYiI6B1L9tmKJLB+90mf9YhXbzoRktlHwLGG2NkBjYQd X-Received: by 10.180.187.232 with SMTP id fv8mr22898488wic.28.1433966997336; Wed, 10 Jun 2015 13:09:57 -0700 (PDT) Received: from scallop.lan (cpc4-aztw19-0-0-cust71.18-1.cable.virginm.net. [82.33.25.72]) by mx.google.com with ESMTPSA id u9sm16105057wju.44.2015.06.10.13.09.55 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Jun 2015 13:09:56 -0700 (PDT) From: Daniel Thompson To: Mike Turquette , Stephen Boyd Subject: [PATCH v3 1/3] dt-bindings: Document the STM32F4 clock bindings Date: Wed, 10 Jun 2015 21:09:36 +0100 Message-Id: <1433966978-24422-2-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 2.4.2 In-Reply-To: <1433966978-24422-1-git-send-email-daniel.thompson@linaro.org> References: <1432327273-6810-1-git-send-email-daniel.thompson@linaro.org> <1433966978-24422-1-git-send-email-daniel.thompson@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150610_131020_025016_1D196C97 X-CRM114-Status: GOOD ( 11.96 ) X-Spam-Score: -0.7 (/) Cc: Mark Rutland , devicetree@vger.kernel.org, Daniel Thompson , linaro-kernel@lists.linaro.org, Russell King , Pawel Moll , Ian Campbell , patches@linaro.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Kamil Lulko , Rob Herring , Maxime Coquelin , Kumar Gala , Andreas Farber , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block. Signed-off-by: Daniel Thompson Acked-by: Maxime Coquelin --- .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt new file mode 100644 index 0000000..fee3205 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt @@ -0,0 +1,65 @@ +STMicroelectronics STM32 Reset and Clock Controller +=================================================== + +The RCC IP is both a reset and a clock controller. This documentation only +describes the clock part. + +Please also refer to clock-bindings.txt in this directory for common clock +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32f42xx-rcc" +- reg: should be register base and length as documented in the + datasheet +- #clock-cells: 2, device nodes should specify the clock in their "clocks" + property, containing a phandle to the clock device node, an index selecting + between gated clocks and other clocks and an index specifying the clock to + use. + +Example: + + rcc: rcc@40023800 { + #clock-cells = <2> + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; + reg = <0x40023800 0x400>; + }; + +Specifying gated clocks +======================= + +The primary index must be set to 0. + +The secondary index is the bit number within the RCC register bank, starting +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). + +It is calculated as: index = register_offset / 4 * 32 + bit_offset. +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). + +Example: + + /* Gated clock, AHB1 bit 0 (GPIOA) */ + ... { + clocks = <&rcc 0 0> + }; + + /* Gated clock, AHB2 bit 4 (CRYP) */ + ... { + clocks = <&rcc 0 36> + }; + +Specifying other clocks +======================= + +The primary index must be set to 1. + +The secondary index is bound with the following magic numbers: + + 0 SYSTICK + 1 FCLK + +Example: + + /* Misc clock, FCLK */ + ... { + clocks = <&rcc 1 1> + };