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[67.207.112.226]) by mx.google.com with ESMTPSA id zt9sm1522439pac.9.2015.06.11.13.08.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 11 Jun 2015 13:08:46 -0700 (PDT) From: Duc Dang To: Bjorn Helgaas Subject: [PATCH 1/1] PCI: X-Gene: Disable Configuration Request Retry Status for X-Gene v1 PCIe Date: Thu, 11 Jun 2015 13:08:14 -0700 Message-Id: <1434053294-10962-1-git-send-email-dhdang@apm.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150611_130912_675170_72103568 X-CRM114-Status: GOOD ( 15.89 ) X-Spam-Score: -2.3 (--) Cc: Ian Campbell , linux-pci@vger.kernel.org, Duc Dang , patches@apm.com, linux-kernel@vger.kernel.org, Marcin Juszkiewicz , linux-arm-kernel@lists.infradead.org, Tanmay Inamdar X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP X-Gene v1 PCIe controller has a bug in Configuration Request Retry Status (CRS) logic: When CPU tries to read Vendor ID and Device ID of not-existed remote device, the controller returns 0xFFFF0001 instead of 0xFFFFFFFF; this will add significant delay in boot time as pci_bus_read_dev_vendor_id will wait for 60 seconds before giving up. So for X-Gene v1 PCIe controllers, disable CRS capability advertisement by clearing CRS Software Visibility bit before returning the Root Capability value to the callers. This is done by implementing X-Gene PCIe specific xgene_pcie_config_read32 for CFG read accesses to replace the generic default pci_generic_config_read32 function. Signed-off-by: Duc Dang Tested-by: Marcin Juszkiewicz Tested-by: Ian Campbell --- drivers/pci/host/pci-xgene.c | 48 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c index ee082c0..741a253 100644 --- a/drivers/pci/host/pci-xgene.c +++ b/drivers/pci/host/pci-xgene.c @@ -59,6 +59,12 @@ #define SZ_1T (SZ_1G*1024ULL) #define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe) +#define ROOT_CAP_AND_CTRL 0x5C + +/* PCIe IP version */ +#define XGENE_PCIE_IP_VER_UNKN 0 +#define XGENE_PCIE_IP_VER_1 1 + struct xgene_pcie_port { struct device_node *node; struct device *dev; @@ -67,6 +73,7 @@ struct xgene_pcie_port { void __iomem *cfg_base; unsigned long cfg_addr; bool link_up; + u32 version; }; static inline u32 pcie_bar_low_val(u32 addr, u32 flags) @@ -140,9 +147,44 @@ static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, return xgene_pcie_get_cfg_base(bus) + offset; } +int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + void __iomem *addr; + struct xgene_pcie_port *port = bus->sysdata; + + addr = bus->ops->map_bus(bus, devfn, where & ~0x3); + if (!addr) { + *val = ~0; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + *val = readl(addr); + /* + * X-Gene v1 PCIe controller has a bug in Configuration Request + * Retry Status (CRS) logic: + * When CPU tries to read Vendor ID and Device ID of not-existed + * remote device, the controller returns 0xFFFF0001 instead of + * 0xFFFFFFFF; this will add significant delay in boot time as + * pci_bus_read_dev_vendor_id will wait for 60 seconds before + * giving up. + * So for X-Gene v1 PCIe controllers, disable CRS capability + * advertisement by clearing CRS Software Visibility bit before + * returning the Root Capability value to the callers. + */ + if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) && + ((where & ~0x3) == ROOT_CAP_AND_CTRL)) + *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16); + + if (size <= 2) + *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); + + return PCIBIOS_SUCCESSFUL; +} + static struct pci_ops xgene_pcie_ops = { .map_bus = xgene_pcie_map_bus, - .read = pci_generic_config_read32, + .read = xgene_pcie_config_read32, .write = pci_generic_config_write32, }; @@ -483,6 +525,10 @@ static int xgene_pcie_probe_bridge(struct platform_device *pdev) port->node = of_node_get(pdev->dev.of_node); port->dev = &pdev->dev; + port->version = XGENE_PCIE_IP_VER_UNKN; + if (of_device_is_compatible(port->node, "apm,xgene-pcie")) + port->version = XGENE_PCIE_IP_VER_1; + ret = xgene_pcie_map_reg(port, pdev); if (ret) return ret;