From patchwork Sat Jun 27 03:02:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 6684641 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 65426C05AC for ; Sat, 27 Jun 2015 03:10:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 67DED2060D for ; Sat, 27 Jun 2015 03:10:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 684CF20609 for ; Sat, 27 Jun 2015 03:10:29 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z8gSQ-0001kC-2d; Sat, 27 Jun 2015 03:07:06 +0000 Received: from mail-pd0-f176.google.com ([209.85.192.176]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Z8gOo-0006w1-Av for linux-arm-kernel@lists.infradead.org; Sat, 27 Jun 2015 03:03:23 +0000 Received: by pdjn11 with SMTP id n11so84892296pdj.0 for ; Fri, 26 Jun 2015 20:03:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Q8tMqFWXzi5zjyQ/Cdbf2jQAKBvcbhOKcnA1NoTufPY=; b=Ty1f7uQ88vun86WFzzcZRZ8UOtaTPsOIddDthKo5klzinH3jXC9xpDofiF/h1z77oJ KH9tIV6x/ocRFf42r/fb/qQuu0Mx3N/b9XVEP1UVN4keHP4luUEnTh209kdwr3Ake3Uu B/K+MZ/DdGMHPIYbUkMhQXKAovTHv38WSc3dEOAKyPBMRsdbHeNimx1iWujiC9Nc/Igf AgIMc+UB7mgmnLrBnukf7qaG1rFI/yv/QtJVUCDDbJs1JbgO3LkfHkavA8gC10GWLhfb IGUC1KzKX60k78JiRXVTkDCzawwZdoFwMMlHxiwSRiVQnqF/xPMZgmhXek4u/nelTqOO YGxQ== X-Gm-Message-State: ALoCoQkSvhcRBDsyo2q433JH9nh9MxB3V6n7bD+1CV7UwTMSd09lTaTc17HnfPUuYyZzwCGuf5TP X-Received: by 10.68.135.100 with SMTP id pr4mr9293209pbb.25.1435374182445; Fri, 26 Jun 2015 20:03:02 -0700 (PDT) Received: from ubuntu.localdomain (c-24-8-37-141.hsd1.co.comcast.net. [24.8.37.141]) by mx.google.com with ESMTPSA id j7sm34787756pdp.83.2015.06.26.20.03.01 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Jun 2015 20:03:02 -0700 (PDT) From: Lina Iyer To: rjw@rjwysocki.net, ulf.hansson@linaro.org, khilman@linaro.org Subject: [PATCH RFC v2 12/16] drivers: qcom: spm: Enable runtime suspend/resume of CPU PM domain Date: Fri, 26 Jun 2015 21:02:32 -0600 Message-Id: <1435374156-19214-13-git-send-email-lina.iyer@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1435374156-19214-1-git-send-email-lina.iyer@linaro.org> References: <1435374156-19214-1-git-send-email-lina.iyer@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150626_200322_467002_7E41ED16 X-CRM114-Status: GOOD ( 19.50 ) X-Spam-Score: -2.6 (--) Cc: k.kozlowski@samsung.com, linux-pm@vger.kernel.org, msivasub@codeaurora.org, geert@linux-m68k.org, Lina Iyer , agross@codeaurora.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On APQ8084 QCOM SoC's, the CPUs are powered by a single rail controlled by the L2 cache power controller (L2 SPM). The L2 power domain supplies power to all the CPUs and L2. It is safe to power down the domain when all the CPUs and the L2 are powered down. Powering down of the domain is done through the finite state machine on the L2 SAW. The L2 SPM can be configured to enter an idle state, when all CPUs enter their idle state. The L2 SPM state machine would turn off the cache and possibly power off the power domain as well. The SPM also guarantees that the h/w is ready for the CPU to resume, when woken up by an interrupt. Define a cluster that holds the SPM and possibly other common cluster elements. The L2 SAW is also the genpd domain provider and the CPUs are the devices attached to the domain. When CPUIdle powers down each CPU, the ARM domain framework would callback to notify that the domain may be powered off. Configure the L2 SPM at that time to flush the L2 cache and turn off the CPU power rail. Signed-off-by: Lina Iyer --- drivers/soc/qcom/spm.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index bef2dfe1..ad1498e 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -24,9 +24,12 @@ #include #include #include +#include #include +#include #include +#include #include #include @@ -79,6 +82,7 @@ struct spm_driver_data { /* Group for domain entities */ struct cluster { struct spm_driver_data *domain_spm; + bool domain_off; }; static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = { @@ -181,7 +185,23 @@ static void spm_set_low_power_mode(struct spm_driver_data *drv, static int qcom_pm_collapse(unsigned long int unused) { - qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON); + int flags = QCOM_SCM_CPU_PWR_DOWN_L2_ON; + int cpu = smp_processor_id(); + bool domain_off; + + /* + * Check if the CPU domain will power off after this CPU + * enters idle. + * L2 cache may be turned off when the domain powers off, + * flush the non-secure cache before calling into secure. + */ + domain_off = per_cpu(cpu_spm_drv, cpu)->domain->domain_off; + if (domain_off) { + flags = QCOM_SCM_CPU_PWR_DOWN_L2_OFF; + flush_cache_all(); + } + + qcom_scm_cpu_power_down(flags); /* * Returns here only if there was a pending interrupt and we did not @@ -293,6 +313,35 @@ static struct cpuidle_ops qcom_cpuidle_ops __initdata = { CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v1, "qcom,kpss-acc-v1", &qcom_cpuidle_ops); CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v2, "qcom,kpss-acc-v2", &qcom_cpuidle_ops); +static int pd_power_on(struct generic_pm_domain *domain) +{ + struct spm_driver_data *drv = per_cpu(cpu_spm_drv, smp_processor_id()); + struct cluster *pmd = drv->domain; + + if (!pmd || !pmd->domain_spm) + return 0; + + pmd->domain_off = false; + spm_set_low_power_mode(pmd->domain_spm, PM_SLEEP_MODE_STBY); + + return 0; +} + +static int pd_power_off(struct generic_pm_domain *domain) +{ + struct spm_driver_data *drv = per_cpu(cpu_spm_drv, smp_processor_id()); + struct cluster *pmd = drv->domain; + + if (!pmd || !pmd->domain_spm) + return 0; + + pmd->domain_off = true; + spm_set_low_power_mode(pmd->domain_spm, PM_SLEEP_MODE_SPC); + + return 0; +} + + /* Match L2 SPM with their affinity level */ static const struct of_device_id cache_spm_table[] = { { }, @@ -418,8 +467,18 @@ static int spm_dev_probe(struct platform_device *pdev) spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); /* We are ready to use the CPU/Cache SPM. */ - if (is_domain_spm) + if (is_domain_spm) { + struct of_phandle_args args; + int ret; + + args.np = pdev->dev.of_node; + args.args_count = 0; + ret = register_platform_domain_handlers(&args, + pd_power_on, pd_power_off); + if (ret) + dev_dbg(&pdev->dev, "Domain callback not registered\n"); cpu_domain[index].domain_spm = drv; + } else per_cpu(cpu_spm_drv, index) = drv;