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client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1BFFO11FD027.mail.protection.outlook.com (10.58.144.90) with Microsoft SMTP Server (TLS) id 15.1.201.10 via Frontend Transport; Mon, 29 Jun 2015 16:17:25 +0000 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.244.45]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t5TGHNcm017369; Mon, 29 Jun 2015 09:17:23 -0700 From: Fabio Estevam To: shawnguo@kernel.org Subject: [PATCH 1/3] ARM: dts: imx6qdl-sabrelite: Allow HDMI and LVDS to work simultaneously Date: Mon, 29 Jun 2015 13:16:53 -0300 Message-ID: <1435594615-9570-1-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.9.1 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BN1BFFO11FD027; 1:G4s5JAIHHvTLW9CEwzhHMPeigPE2DOaza7X9ULHdExDVByDOapyuznE+1/BMkJ7jgZdkliZEhyJF8IsysWid/h04su+aRIr6d3n6617QP679DVpCRRV8VdEhwCVzwzGYg0XczgmFXcBQ5gHF2JdsVfRGoK2oyBt7tsQwbWWDgnmdAOGdp1XDbTwGr6BzpCj8CRCCE2TiUQw9nNM0gxyuzOA8WtudivMXd04k/0hS+CMVXnhvN+wVtHUcvqQsVcdCVR4kmhO6R8RBojxl5AJ5ACKGsi55wgQd5f+Cxb1wsBhgOS+7valbfGqFpGsmOa9Mactj7CSFmd7ReyOiRV+J9w== X-Forefront-Antispam-Report: CIP:192.88.168.50; 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Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be driven from independent sources. With this change the LDB pixel clock goes to 68.57 MHz, which is still within the valid range for the HSD100PXN1 LVDS panel. Signed-off-by: Fabio Estevam Tested-by: Gary Bisson Acked-by: Philipp Zabel --- arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index e00c44f..d87e71c 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -148,6 +148,13 @@ status = "okay"; }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + &ecspi1 { fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>;