From patchwork Fri Jul 3 14:32:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 6715941 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 603629F2F0 for ; Fri, 3 Jul 2015 14:37:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 776A5206CB for ; Fri, 3 Jul 2015 14:37:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B16F207F0 for ; Fri, 3 Jul 2015 14:37:20 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZB23P-0006MY-R0; Fri, 03 Jul 2015 14:34:59 +0000 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZB21b-0005x7-UO for linux-arm-kernel@lists.infradead.org; Fri, 03 Jul 2015 14:33:08 +0000 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id t63ETWZw030804; Fri, 3 Jul 2015 07:32:46 -0700 Received: from sc-owa04.marvell.com ([199.233.58.150]) by mx0a-0016f401.pphosted.com with ESMTP id 1vbggfav2c-1 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT); Fri, 03 Jul 2015 07:32:46 -0700 Received: from maili.marvell.com (10.93.76.83) by SC-OWA04.marvell.com (10.93.76.33) with Microsoft SMTP Server id 8.3.327.1; Fri, 3 Jul 2015 07:32:45 -0700 Received: from xhacker.marvell.com (unknown [10.37.135.134]) by maili.marvell.com (Postfix) with ESMTP id B9BB03F703F; Fri, 3 Jul 2015 07:32:44 -0700 (PDT) From: Jisheng Zhang To: , Subject: [PATCH 1/2] irqchip: dw-apb-ictl: add private data structure Date: Fri, 3 Jul 2015 22:32:23 +0800 Message-ID: <1435933944-2131-2-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1435933944-2131-1-git-send-email-jszhang@marvell.com> References: <1435933944-2131-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2015-07-03_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 kscore.is_bulkscore=0 kscore.compositescore=1 compositescore=0.9 suspectscore=2 malwarescore=0 phishscore=0 bulkscore=0 kscore.is_spamscore=0 rbsscore=0.9 spamscore=0 urlsuspectscore=0.9 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1506180000 definitions=main-1507030241 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150703_073307_997374_45B8C01E X-CRM114-Status: GOOD ( 13.01 ) X-Spam-Score: -2.6 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jisheng Zhang , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds struct dw_apb_ictl_priv definition, now it only has one member: the irq domain. Then make the generic irq chip gc->private to point to the struct. This is to prepare for the next patch which will implement irq_set_affinity. Signed-off-by: Jisheng Zhang --- drivers/irqchip/irq-dw-apb-ictl.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-dw-apb-ictl.c b/drivers/irqchip/irq-dw-apb-ictl.c index 53bb732..8bef7f7 100644 --- a/drivers/irqchip/irq-dw-apb-ictl.c +++ b/drivers/irqchip/irq-dw-apb-ictl.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "irqchip.h" @@ -26,11 +27,16 @@ #define APB_INT_FINALSTATUS_L 0x30 #define APB_INT_FINALSTATUS_H 0x34 +struct dw_apb_ictl_priv { + struct irq_domain *domain; +}; + static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc) { struct irq_chip *chip = irq_get_chip(irq); struct irq_chip_generic *gc = irq_get_handler_data(irq); - struct irq_domain *d = gc->private; + struct dw_apb_ictl_priv *priv = gc->private; + struct irq_domain *d = priv->domain; u32 stat; int n; @@ -71,27 +77,34 @@ static int __init dw_apb_ictl_init(struct device_node *np, unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; struct resource r; struct irq_domain *domain; + struct dw_apb_ictl_priv *priv; struct irq_chip_generic *gc; void __iomem *iobase; int ret, nrirqs, irq; u32 reg; + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + /* Map the parent interrupt for the chained handler */ irq = irq_of_parse_and_map(np, 0); if (irq <= 0) { pr_err("%s: unable to parse irq\n", np->full_name); - return -EINVAL; + ret = -EINVAL; + goto err_free; } ret = of_address_to_resource(np, 0, &r); if (ret) { pr_err("%s: unable to get resource\n", np->full_name); - return ret; + goto err_free; } if (!request_mem_region(r.start, resource_size(&r), np->full_name)) { pr_err("%s: unable to request mem region\n", np->full_name); - return -ENOMEM; + ret = -ENOMEM; + goto err_free; } iobase = ioremap(r.start, resource_size(&r)); @@ -138,7 +151,8 @@ static int __init dw_apb_ictl_init(struct device_node *np, } gc = irq_get_domain_generic_chip(domain, 0); - gc->private = domain; + priv->domain = domain; + gc->private = priv; gc->reg_base = iobase; gc->chip_types[0].regs.mask = APB_INT_MASK_L; @@ -164,6 +178,8 @@ err_unmap: iounmap(iobase); err_release: release_mem_region(r.start, resource_size(&r)); +err_free: + kfree(priv); return ret; } IRQCHIP_DECLARE(dw_apb_ictl,