From patchwork Mon Jul 6 07:09:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "majun (F)" X-Patchwork-Id: 6720131 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 52AC9C05AC for ; Mon, 6 Jul 2015 07:13:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 63E432062C for ; Mon, 6 Jul 2015 07:13:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 760A4203E9 for ; Mon, 6 Jul 2015 07:13:09 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZC0Yp-0008Ji-RG; Mon, 06 Jul 2015 07:11:27 +0000 Received: from szxga03-in.huawei.com ([119.145.14.66]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZC0Ym-00087S-1f for linux-arm-kernel@lists.infradead.org; Mon, 06 Jul 2015 07:11:25 +0000 Received: from 172.24.2.119 (EHLO szxeml431-hub.china.huawei.com) ([172.24.2.119]) by szxrg03-dlp.huawei.com (MOS 4.4.3-GA FastPath queued) with ESMTP id BIS32336; Mon, 06 Jul 2015 15:09:28 +0800 (CST) Received: from localhost (10.177.236.124) by szxeml431-hub.china.huawei.com (10.82.67.208) with Microsoft SMTP Server id 14.3.158.1; Mon, 6 Jul 2015 15:09:17 +0800 From: Ma Jun To: , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 3/3] dt-binding:Documents the mbigen bindings Date: Mon, 6 Jul 2015 15:09:08 +0800 Message-ID: <1436166548-34920-4-git-send-email-majun258@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1436166548-34920-1-git-send-email-majun258@huawei.com> References: <1436166548-34920-1-git-send-email-majun258@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.236.124] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020201.559A29A8.0166, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2013-05-26 15:14:31, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 540e57aa958d353ccb982392d8adb05a X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150706_001124_430353_CB213DE8 X-CRM114-Status: GOOD ( 14.37 ) X-Spam-Score: -4.8 (----) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the mbigen msi interrupt controller bindings document Change in v3: ---Change the compatible string ---Change the interrupt cells definition. Signed-off-by: Ma Jun --- Documentation/devicetree/bindings/arm/mbigen.txt | 65 ++++++++++++++++++++++ 1 files changed, 65 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt diff --git a/Documentation/devicetree/bindings/arm/mbigen.txt b/Documentation/devicetree/bindings/arm/mbigen.txt new file mode 100644 index 0000000..cf92ef8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mbigen.txt @@ -0,0 +1,65 @@ +Hisilicon mbigen device tree bindings. +======================================= + +Mbigen means: message based interrupt generator. + +MBI is kind of msi interrupt only used on Non-PCI devices. + +To reduce the wired interrupt number connected to GIC, +Hisilicon designed mbigen to collect and generate interrupt. + + +Non-pci devices can connect to mbigen and gnerate the inteerrupt +by wirtting ITS register. + +The mbigen and devices connect to mbigen have the following properties: + + +Mbigen required properties: +------------------------------------------- +-compatible: Should be "hisilicon,mbigen-v2" +-msi-parent: should specified the ITS mbigen connected +-interrupt controller: Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value is 5 now. + + The 1st cell is the device id. + The 2nd cell is the totall interrupt number of this device + The 3rd cell is the hardware pin number of the interrupt. + This value depends on the Soc design. + The 4th cell is the mbigen node number. This value should refer to the + vendor soc specification. + The 5th cell is the interrupt trigger type, encoded as follows: + 1 = edge triggered + 4 = level triggered + +- reg: Specifies the base physical address and size of the ITS + registers. + +Examples: + + mbigen_dsa: interrupt-controller@c0080000 { + compatible = "hisilicon,mbigen-v2"; + msi-parent = <&its_dsa>; + interrupt-controller; + #interrupt-cells = <5>; + reg = <0xc0080000 0x10000>; + }; + +Device connect to mbigen required properties: +---------------------------------------------------- +-interrupt-parent: Specifies the mbigen node which device connected. +-interrupts:specifies the interrupt source.The first cell is hwirq num, the + second number is trigger type. + +Examples: + smmu_dsa { + compatible = "arm,smmu-v3"; + reg = <0x0 0xc0040000 0x0 0x20000>; + interrupt-parent = <&mbigen_dsa>; + interrupts = <0x40b20 3 78 6 1>, + <0x40b20 3 79 6 1>, + <0x40b20 3 80 6 1>; + smmu-cb-memtype = <0x0 0x1>; + }; +