diff mbox

arm: dts: dra7: arch timer sits in always-on power domain

Message ID 1436820101-2172-1-git-send-email-balbi@ti.com (mailing list archive)
State New, archived
Headers show

Commit Message

Felipe Balbi July 13, 2015, 8:41 p.m. UTC
According to DRA7x TRM section 4.3.5 Realtime Counter (Master Counter),
the realtime counter sits in the Wakeup Always-On Power domain.
Furthermore, the counter will automatically switch the 32K clock source
when MPU goes into standby and automatically switch back to SYS_CLK or
ABE_LP when MPU goes out of standby.

Signed-off-by: Felipe Balbi <balbi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 1 +
 1 file changed, 1 insertion(+)

Comments

Nishanth Menon July 13, 2015, 8:53 p.m. UTC | #1
On Mon, Jul 13, 2015 at 3:41 PM, Felipe Balbi <balbi@ti.com> wrote:
> According to DRA7x TRM section 4.3.5 Realtime Counter (Master Counter),
> the realtime counter sits in the Wakeup Always-On Power domain.
> Furthermore, the counter will automatically switch the 32K clock source
> when MPU goes into standby and automatically switch back to SYS_CLK or
> ABE_LP when MPU goes out of standby.
>
> Signed-off-by: Felipe Balbi <balbi@ti.com>


Acked-by: NIshanth Menon <nm@ti.com>

> ---
>  arch/arm/boot/dts/dra7.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 8f1e25bcecbd..c1e6fd82485f 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -50,6 +50,7 @@
>                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
>                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
>                 interrupt-parent = <&gic>;
> +               always-on;
>         };
>
>         gic: interrupt-controller@48211000 {
> --
> 2.4.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Tony Lindgren July 14, 2015, 4:49 a.m. UTC | #2
* Nishanth Menon <nm@ti.com> [150713 13:56]:
> On Mon, Jul 13, 2015 at 3:41 PM, Felipe Balbi <balbi@ti.com> wrote:
> > According to DRA7x TRM section 4.3.5 Realtime Counter (Master Counter),
> > the realtime counter sits in the Wakeup Always-On Power domain.
> > Furthermore, the counter will automatically switch the 32K clock source
> > when MPU goes into standby and automatically switch back to SYS_CLK or
> > ABE_LP when MPU goes out of standby.

That's good to hear. Is that the case also for 5432?

Regards,

Tony
Tony Lindgren July 14, 2015, 7:05 a.m. UTC | #3
* Tony Lindgren <tony@atomide.com> [150713 21:52]:
> * Nishanth Menon <nm@ti.com> [150713 13:56]:
> > On Mon, Jul 13, 2015 at 3:41 PM, Felipe Balbi <balbi@ti.com> wrote:
> > > According to DRA7x TRM section 4.3.5 Realtime Counter (Master Counter),
> > > the realtime counter sits in the Wakeup Always-On Power domain.
> > > Furthermore, the counter will automatically switch the 32K clock source
> > > when MPU goes into standby and automatically switch back to SYS_CLK or
> > > ABE_LP when MPU goes out of standby.
> 
> That's good to hear. Is that the case also for 5432?

Adding into omap-for-v4.2/fixes, if 5432 supports it too it
can be patched separately.

Regards,

Tony
Mark Rutland July 15, 2015, 9:24 a.m. UTC | #4
On Mon, Jul 13, 2015 at 09:41:41PM +0100, Felipe Balbi wrote:
> According to DRA7x TRM section 4.3.5 Realtime Counter (Master Counter),
> the realtime counter sits in the Wakeup Always-On Power domain.
> Furthermore, the counter will automatically switch the 32K clock source
> when MPU goes into standby and automatically switch back to SYS_CLK or
> ABE_LP when MPU goes out of standby.

While the counter is in an always-on domain (the architecture mandates
this) I don't think that applies to the timers (i.e. the comparators
within a CPU), which are almost certainly not in an always-on domain.

I suspect that this is incorrect, and it will be very painful to debug
if it is...

Thanks,
Mark.

> 
> Signed-off-by: Felipe Balbi <balbi@ti.com>
> ---
>  arch/arm/boot/dts/dra7.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index 8f1e25bcecbd..c1e6fd82485f 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -50,6 +50,7 @@
>  			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
>  			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
>  		interrupt-parent = <&gic>;
> +		always-on;
>  	};
>  
>  	gic: interrupt-controller@48211000 {
> -- 
> 2.4.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
Tony Lindgren July 15, 2015, 10 a.m. UTC | #5
* Mark Rutland <mark.rutland@arm.com> [150715 02:27]:
> On Mon, Jul 13, 2015 at 09:41:41PM +0100, Felipe Balbi wrote:
> > According to DRA7x TRM section 4.3.5 Realtime Counter (Master Counter),
> > the realtime counter sits in the Wakeup Always-On Power domain.
> > Furthermore, the counter will automatically switch the 32K clock source
> > when MPU goes into standby and automatically switch back to SYS_CLK or
> > ABE_LP when MPU goes out of standby.
> 
> While the counter is in an always-on domain (the architecture mandates
> this) I don't think that applies to the timers (i.e. the comparators
> within a CPU), which are almost certainly not in an always-on domain.
> 
> I suspect that this is incorrect, and it will be very painful to debug
> if it is...

OK good point. And there would have to be some wake-up line wired to the
IO chain or the PMIC in this case if the comparator was always on.

Dropping this patch for now anyways.

Regards,

Tony
diff mbox

Patch

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 8f1e25bcecbd..c1e6fd82485f 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -50,6 +50,7 @@ 
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 		interrupt-parent = <&gic>;
+		always-on;
 	};
 
 	gic: interrupt-controller@48211000 {