From patchwork Wed Jul 15 14:38:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 6799191 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7CACF9F2F0 for ; Wed, 15 Jul 2015 14:41:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9D99D2061C for ; Wed, 15 Jul 2015 14:41:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 189CD205F4 for ; Wed, 15 Jul 2015 14:41:38 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZFNpx-0006Hc-VY; Wed, 15 Jul 2015 14:39:05 +0000 Received: from foss.arm.com ([217.140.101.70]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZFNpv-0006EB-JB for linux-arm-kernel@lists.infradead.org; Wed, 15 Jul 2015 14:39:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C8EB975; Wed, 15 Jul 2015 07:38:58 -0700 (PDT) Received: from e103737-lin.cambridge.arm.com (e103737-lin.cambridge.arm.com [10.1.207.150]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9B75D3F317; Wed, 15 Jul 2015 07:38:36 -0700 (PDT) From: Sudeep Holla To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] irqchip: gic: enable SKIP_SET_WAKE and MASK_ON_SUSPEND Date: Wed, 15 Jul 2015 15:38:28 +0100 Message-Id: <1436971109-20189-1-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150715_073903_642962_D3CEBA86 X-CRM114-Status: GOOD ( 12.30 ) X-Spam-Score: -8.3 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , Jason Cooper , Marc Zyngier , Linus Walleij , Magnus Damm , Michal Simek , Simon Horman , Geert Uytterhoeven , Sudeep Holla , Gregory CLEMENT , Thomas Gleixner MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The GIC controller doesn't provides any facility to configure the wakeup sources. For the same reason, GIC chip implementation can't provide irq_set_wake functionality, but that results in the irqchip core preventing the systems from entering sleep states like "suspend to RAM". The GICv1/v2 controllers supports wakeup events. It signals these wakeup events even when CPU interface is disabled which means the wakeup outputs are always enabled with the required logic in always-on domain. An implementation can powerdown the GIC completely, but then the wake-up must be relayed to some control logic within the power controller that acts as wake-up interrupt controller. Setting the IRQCHIP_SKIP_SET_WAKE flags will ensure that the interrupts from GIC can work as wakeup interrupts and resume from suspend-to-{idle, ram}. The wakeup interrupt sources need to use enable_irq_wake() and the irqchip core will then set the IRQD_WAKEUP_STATE flag. Also it's always safer to mask all the non wakeup interrupts are masked at the chip level when suspending. The irqchip infrastructure can handle masking of those interrupts at the chip level. The chip implementation just have to indicate that with IRQCHIP_MASK_ON_SUSPEND. This patch enables IRQCHIP_SKIP_SET_WAKE and IRQCHIP_MASK_ON_SUSPEND so that the irqchip core allows and handles the power managemant wake up modes. Cc: Thomas Gleixner Cc: Jason Cooper Cc: Marc Zyngier Signed-off-by: Sudeep Holla --- drivers/irqchip/irq-gic.c | 4 +++- drivers/irqchip/irq-hip04.c | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) Hi, Most of the platforms with GICv1/v2 implementing S2R are setting up these flags already. This patch moves the logic to the GIC driver so that any further duplication is avoided. Regards, Sudeep -- 1.9.1 diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4dd88264dff5..eda24604a0f3 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -324,7 +324,9 @@ static struct irq_chip gic_chip = { #endif .irq_get_irqchip_state = gic_irq_get_irqchip_state, .irq_set_irqchip_state = gic_irq_set_irqchip_state, - .flags = IRQCHIP_SET_TYPE_MASKED, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, }; void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) diff --git a/drivers/irqchip/irq-hip04.c b/drivers/irqchip/irq-hip04.c index 0cae45d10695..91a9fa3d3b11 100644 --- a/drivers/irqchip/irq-hip04.c +++ b/drivers/irqchip/irq-hip04.c @@ -202,7 +202,9 @@ static struct irq_chip hip04_irq_chip = { #ifdef CONFIG_SMP .irq_set_affinity = hip04_irq_set_affinity, #endif - .flags = IRQCHIP_SET_TYPE_MASKED, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, }; static u16 hip04_get_cpumask(struct hip04_irq_data *intc)