From patchwork Mon Jul 27 19:29:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shenwei Wang X-Patchwork-Id: 6876181 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 88A279F38B for ; Mon, 27 Jul 2015 19:33:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3A6FD204AD for ; Mon, 27 Jul 2015 19:33:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 059DC20458 for ; Mon, 27 Jul 2015 19:33:14 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZJo73-0003Pc-VP; Mon, 27 Jul 2015 19:31:01 +0000 Received: from mail-by2on0107.outbound.protection.outlook.com ([207.46.100.107] helo=na01-by2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZJo70-0003KX-80 for linux-arm-kernel@lists.infradead.org; Mon, 27 Jul 2015 19:30:59 +0000 Received: from BLUPR0301CA0032.namprd03.prod.outlook.com (10.162.113.170) by BN3PR03MB1366.namprd03.prod.outlook.com (10.163.34.152) with Microsoft SMTP Server (TLS) id 15.1.225.19; Mon, 27 Jul 2015 19:30:36 +0000 Received: from BN1AFFO11FD056.protection.gbl (2a01:111:f400:7c10::120) by BLUPR0301CA0032.outlook.office365.com (2a01:111:e400:5259::42) with Microsoft SMTP Server (TLS) id 15.1.225.19 via Frontend Transport; Mon, 27 Jul 2015 19:30:36 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD056.mail.protection.outlook.com (10.58.53.71) with Microsoft SMTP Server (TLS) id 15.1.231.11 via Frontend Transport; Mon, 27 Jul 2015 19:30:36 +0000 Received: from [tx30smr01.am.freescale.net (B38339-11.am.freescale.net [10.81.93.199]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t6RJUJY7012880; Mon, 27 Jul 2015 12:30:35 -0700 From: Shenwei Wang To: , , Subject: [PATCH v7 1/2] irqchip: imx-gpcv2: IMX GPCv2 driver for wakeup sources Date: Mon, 27 Jul 2015 14:29:59 -0500 Message-ID: <1438025400-5919-2-git-send-email-shenwei.wang@freescale.com> X-Mailer: git-send-email 2.5.0.rc2 In-Reply-To: <1438025400-5919-1-git-send-email-shenwei.wang@freescale.com> References: <1438025400-5919-1-git-send-email-shenwei.wang@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BN1AFFO11FD056; 1:DkFEeideHoHA2IPnOu0uTm9PqUIIMyMc+NYVPiDVqbjhrPPl/YkZFLYXC3Fz46T3hidxa5WJQuUcwmwJ/Mvc3l/Xq2jd0OMJunqwJeRW25bFue3vSP3cwwKRZ38eaF2qrmpULytUi2AAyR3EyKtHS8l9TAfp2r7MAqGgOy5MCox3kff3xTstZ6Gja2IJTPqRVaJEZn6rtgdoE2B/MuYe6d8pH/A6wWYPJEiGWEs1y622hhKHxA5lRCFzltAi9My0bC/IgCkvDGZm/iRbCMS/aQgvBNs9gFF4isqhnx/RJtg/AKj8r+R2SthmH9zWqDhlzHq5OSTR/r/JoKPCP9nRDg== X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(2980300002)(339900001)(199003)(189002)(19580405001)(5001770100001)(77096005)(36756003)(106466001)(47776003)(50986999)(62966003)(77156002)(2950100001)(105606002)(92566002)(229853001)(85426001)(2201001)(48376002)(50466002)(86362001)(46102003)(87936001)(6806004)(76176999)(5001960100002)(33646002)(50226001)(107886002)(104016003)(189998001)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:BN3PR03MB1366; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Exchange-Diagnostics: 1; BN3PR03MB1366; 2:NpLFO7OQOwnTk0zBQtnGD5PhmRGqc9koxscsZLOrxkNAOS6nTcox7+o1Seiu18i4ol5qJUVW+/48BaGGhDgChGqa+KN0y78QgyRwx8onZAN+8l1g8f4fQ1SfSaoGl669CINI3oMk8Nm/Qy8+YUcxWnUCBdmmJWZUJv21xaOI/ac=; 3:aBA6v1oRgDmr3TZHtgwNa9OhGR4ovw7cXkUYOgHAd4ZGoBcXUWfNA3RrPiVilKnW0cN/WCSKUHo8bZLILxmpXed70pDCadt1vZJq9/1XvJMMRCSA8rss5XW0cqXa75uhV/buLeqvWt61GypN40a49xuevBL8+v+gUf8P6i4D5UbGsg+E9pOzxn1ZoRJ7Wbl+nFdNONtC4JExuV9/3MZrUEOm0KGXx+GJlIPM9DC9H44=; 25:bRFsUWZy4xPwZsHrYk+e0nA0O3erDNFMsCJmFf9Z5H6VUHTRdteRUaV+etV4gxOJjqeanjwNWfPHK5DQwejh+PKDvry5oEtvSQCBAhgOzqkr6idpMk39cfmb8E3MBju0tktXjLQEXih1qxqsK72P1SZ1SueRG98yHKnUT6x/jdWcr0b7KNqmuq76z1o8JIj+YD1IcVqstQJWhGB8zHpzS5JhFX1flE09SeqoD8w4ZTOW2ETZNEBqGahsWzwHM08W X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN3PR03MB1366; X-Microsoft-Exchange-Diagnostics: 1; BN3PR03MB1366; 20:/x5+hsXGY6h4hWZlHLtzcZw+I7Jy9id1ovtxAd6MsjkfvnLbv0F3GNcBd4R8+1eqvLrPyFV6etIoMQT8fMpYgKSQvdSDALRckqCsfgm0Z5XfIxZMHG7GTVQLcc0SN0ICkSwqPg/kcWJZMXSLO0PMk42oYiZ/V/HPJdd1xbSVEOxmPjOaATl+OZXFWheP73bHyasejp8AjbeaV6DQblc3R2syEeOEZdWe0Djomjdhtk5T3qrJZ82DNenM2NrWzW/zN1qrRX3IvylNUwyRnv6C9QgfEtmdBcXSHUcIlAQlUjacmYOvLluFVNjwIvx0lQlzfbacxzmauc2U48TkgLp++gOdtOUBlxzlvn6clS/vbxI=; 4:LMpHWE36KHyIPYo0+DfUlApxfOVNp8X6+CQIJ8fs0jqA4ebnwXhLMWfjJZa+mllnhJBdY7Qghs3n33phfmqe0gDyR82Uii1DuimEo0B3z2OsFNBhtE+QIFsNQ8JwKR5xUBQlUJokm004K0teRX79z8+DBQbMS6E7WtjszMxNdURFuf/Gwo5erani6ZXf6k4EEYKUXyacQGLiUmgTQS9HGJTiZ2DUsjM4Av73luIOXQbgkZU5TDepmtgmrGQqDyLMKvxm2EY6GvEp+MsiRpDS6rq/0+ECIxTcqaMig8yVL4Q= BN3PR03MB1366: X-MS-Exchange-Organization-RulesExecuted X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:BN3PR03MB1366; BCL:0; PCL:0; RULEID:; SRVR:BN3PR03MB1366; X-Forefront-PRVS: 0650714AAA X-Microsoft-Exchange-Diagnostics: 1; BN3PR03MB1366; 23:cTDZ+O8mU4fA77jjmhIBPAWgMQ7sdzkdzPW5nGrS75czQxEdwlIgCLaHe1/pAVAiwX7d5q0XfjZq7ZVspxCR+phtLU6mP7Ns/hVL4khdgzPDWdjncHEPrX+Yxz2wpNz35cr0tKeoLpxOkKRQWUUa6y7cXW7hn7pjQXtnRmWmnqLC6+Rj6ENY5OpAesKG059PGVwl88gjMDR7rDbLHRqY+fdbQpahGiv66WWadTdbnMDENJAMB4x8Ov/ZjLRfziASIGxxOWC83uH8+yMMuVZiEUlCknIskhJ5w9YWTEVhk6EinVrM2OAyPNdZndxMrdH2U+qyNar8cmzABffA9p6kNU3wKgBbjO5QsJCFT85Q0sXw23orjjbfNH/wmA0QNnJCJZIKCLRTCOgCLDOKPjBEV3H/PTo0w8kNVxx8PMIYX9sq9RIWjRfGaKe1rOiQi2OmccdPUz/qlyaeQbrH6N5eNyiycVaB0oanPBaCNm4CPjJfuGEXVFfxnXTNyCYBCkV3FARDd+IEr3ZvCq44aZoJP1wH3qdALxId8B4SJ2Os5ZEz5i0FekxQq+mFocfgnYMQ/2OKBjqpNerqumMFt+HkHXl3jJze9WdCJ4Pc2u62Cepb5jJ8Ydw0Pcl3dOGD1lMONYLuIpvO1gXrRQQlN2QIGJm9bX7SPYlVjVftHC4Hdqvd7MNJU/tF4w1ApyiS1mauTirBbUvmOMjqlNWR9GV3CULVnq+Qpgq/QA8srBROfwbXN8qM4wwN4kTMtg0U69tMBR961SAbfjUlMZIyL0fGdSRxinzBi0EEhbq2uo/iBN4cBMLNDduK7gk2nui760adQVF1r38hPXimWWttSfjWoVbkHYJ4At7iX9BEgZDUt+cqPbOnuITkgoNKY0fKZ6aUGZK3Irf55+PWgixm7FX5Xi+lXx6dsnhNZYlmDvsqxUk= X-Microsoft-Exchange-Diagnostics: 1; BN3PR03MB1366; 5:De4hEssE626CKvgbEVt1bedtv08tQZps9zAVnpmWaur3PsnsK5l+fyOGbVDJ0Wq+vVPWxP/rSHdhPBIRrnthyMhqgYWK376a7OSmvicnK5dszRcjxW3RVs0NrwQ/zkgIy5garrXlnqBPCgKD3wDsig==; 24:409IMBUgcVL3yR5COKZCkPecrq1aimuqSPGYMBDFwP52F1jhaEOHM1NlH1z9VkKyDuEQ2GRFDajItwVnIdfQ9LOREoz7OfZUrABL1eEy994=; 20:v+kH3IrxvQKd5ks/+hELLWffyd7x8N7Ti+irsBiWlLbQYRIhdujFs6DPMclctYrXJdVDUy12n6BrOrVAVUZjWw== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jul 2015 19:30:36.5528 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB1366 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150727_123058_372388_0F70BDA0 X-CRM114-Status: GOOD ( 32.22 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: b20788@freescale.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP IMX7D contains a new version of GPC IP block (GPCv2). It has two major functions: power management and wakeup source management. This patch adds a new irqchip driver to manage the interrupt wakeup sources on IMX7D. When the system is in WFI (wait for interrupt) mode, this GPC block will be the first block on the platform to be activated and signaled. Under normal wait mode during cpu idle, the system can be woke up by any enabled interrupts. Under standby or suspend mode, the system can only be woke up by the pre-defined wakeup sources. Signed-off-by: Shenwei Wang Signed-off-by: Anson Huang --- drivers/irqchip/Kconfig | 7 ++ drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-imx-gpcv2.c | 254 ++++++++++++++++++++++++++++++++++++++++ include/soc/imx/gpcv2.h | 25 ++++ 4 files changed, 287 insertions(+) create mode 100644 drivers/irqchip/irq-imx-gpcv2.c create mode 100644 include/soc/imx/gpcv2.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 120d815..3fc0fac 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -177,3 +177,10 @@ config RENESAS_H8300H_INTC config RENESAS_H8S_INTC bool select IRQ_DOMAIN + +config IMX_GPCV2 + bool + select IRQ_DOMAIN + help + Enables the wakeup IRQs for IMX platforms with GPCv2 block + diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index b8d4e96..8eb5f60 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -52,3 +52,4 @@ obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o +obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c new file mode 100644 index 0000000..3084f16 --- /dev/null +++ b/drivers/irqchip/irq-imx-gpcv2.c @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include + +#include + +#define GPC_MAX_IRQS (IMR_NUM * 32) + +#define GPC_IMR1_CORE0 0x30 +#define GPC_IMR1_CORE1 0x40 + +struct imx_gpcv2_irq *gpcv2_irq_instance; + +static int gpcv2_wakeup_source_save(void) +{ + struct imx_gpcv2_irq *cd; + void __iomem *reg; + int i; + + cd = gpcv2_irq_instance; + if (!cd) + return 0; + + for (i = 0; i < IMR_NUM; i++) { + reg = cd->gpc_base + cd->cpu2wakeup + i * 4; + cd->enabled_irqs[i] = readl_relaxed(reg); + writel_relaxed(cd->wakeup_sources[i], reg); + } + + return 0; +} + +static void gpcv2_wakeup_source_restore(void) +{ + struct imx_gpcv2_irq *cd; + void __iomem *reg; + int i; + + cd = gpcv2_irq_instance; + if (!cd) + return; + + for (i = 0; i < IMR_NUM; i++) { + reg = cd->gpc_base + cd->cpu2wakeup + i * 4; + writel_relaxed(cd->enabled_irqs[i], reg); + cd->wakeup_sources[i] = ~0; + } +} + +static struct syscore_ops imx_gpcv2_syscore_ops = { + .suspend = gpcv2_wakeup_source_save, + .resume = gpcv2_wakeup_source_restore, +}; + +static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct imx_gpcv2_irq *cd = d->chip_data; + unsigned int idx = d->hwirq / 32; + unsigned long flags; + void __iomem *reg; + u32 mask, val; + + raw_spin_lock_irqsave(&cd->rlock, flags); + reg = cd->gpc_base + cd->cpu2wakeup + idx * 4; + mask = 1 << d->hwirq % 32; + val = cd->wakeup_sources[idx]; + + cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask); + raw_spin_unlock_irqrestore(&cd->rlock, flags); + + /* + * Do *not* call into the parent, as the GIC doesn't have any + * wake-up facility... + */ + + return 0; +} + + +static void imx_gpcv2_irq_unmask(struct irq_data *d) +{ + struct imx_gpcv2_irq *cd = d->chip_data; + void __iomem *reg; + u32 val; + + raw_spin_lock(&cd->rlock); + reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; + val = readl_relaxed(reg); + val &= ~(1 << d->hwirq % 32); + writel_relaxed(val, reg); + raw_spin_unlock(&cd->rlock); + + irq_chip_unmask_parent(d); +} + +static void imx_gpcv2_irq_mask(struct irq_data *d) +{ + struct imx_gpcv2_irq *cd = d->chip_data; + void __iomem *reg; + u32 val; + + raw_spin_lock(&cd->rlock); + reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; + val = readl_relaxed(reg); + val |= 1 << (d->hwirq % 32); + writel_relaxed(val, reg); + raw_spin_unlock(&cd->rlock); + + irq_chip_mask_parent(d); +} + + +static struct irq_chip imx_gpcv2_irq_chip = { + .name = "GPCv2", + .irq_eoi = irq_chip_eoi_parent, + .irq_mask = imx_gpcv2_irq_mask, + .irq_unmask = imx_gpcv2_irq_unmask, + .irq_set_wake = imx_gpcv2_irq_set_wake, + .irq_retrigger = irq_chip_retrigger_hierarchy, +#ifdef CONFIG_SMP + .irq_set_affinity = irq_chip_set_affinity_parent, +#endif +}; + +static int imx_gpcv2_domain_xlate(struct irq_domain *domain, + struct device_node *controller, + const u32 *intspec, + unsigned int intsize, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + /* Shouldn't happen, really... */ + if (domain->of_node != controller) + return -EINVAL; + + /* Not GIC compliant */ + if (intsize != 3) + return -EINVAL; + + /* No PPI should point to this domain */ + if (intspec[0] != 0) + return -EINVAL; + + *out_hwirq = intspec[1]; + *out_type = intspec[2]; + return 0; +} + +static int imx_gpcv2_domain_alloc(struct irq_domain *domain, + unsigned int irq, unsigned int nr_irqs, + void *data) +{ + struct of_phandle_args *args = data; + struct of_phandle_args parent_args; + irq_hw_number_t hwirq; + int i; + + /* Not GIC compliant */ + if (args->args_count != 3) + return -EINVAL; + + /* No PPI should point to this domain */ + if (args->args[0] != 0) + return -EINVAL; + + /* Can't deal with this */ + hwirq = args->args[1]; + if (hwirq >= GPC_MAX_IRQS) + return -EINVAL; + + for (i = 0; i < nr_irqs; i++) { + irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i, + &imx_gpcv2_irq_chip, domain->host_data); + } + parent_args = *args; + parent_args.np = domain->parent->of_node; + return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args); +} + +static struct irq_domain_ops imx_gpcv2_irq_domain_ops = { + .xlate = imx_gpcv2_domain_xlate, + .alloc = imx_gpcv2_domain_alloc, + .free = irq_domain_free_irqs_common, +}; + + + +static int __init imx_gpcv2_irqchip_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *parent_domain, *domain; + struct imx_gpcv2_irq *cd; + int i; + + if (!parent) { + pr_err("%s: no parent, giving up\n", node->full_name); + return -ENODEV; + } + + parent_domain = irq_find_host(parent); + if (!parent_domain) { + pr_err("%s: unable to get parent domain\n", node->full_name); + return -ENXIO; + } + + cd = kzalloc(sizeof(struct imx_gpcv2_irq), GFP_KERNEL); + + cd->gpc_base = of_iomap(node, 0); + if (!cd->gpc_base) { + pr_err("fsl-gpcv2: unable to map gpc registers\n"); + kfree(cd); + return -ENOMEM; + } + + domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS, + node, &imx_gpcv2_irq_domain_ops, cd); + if (!domain) { + iounmap(cd->gpc_base); + kfree(cd); + return -ENOMEM; + } + irq_set_default_host(domain); + + /* Initially mask all interrupts */ + for (i = 0; i < IMR_NUM; i++) { + writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4); + writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4); + cd->wakeup_sources[i] = ~0; + } + + /* Let CORE0 as the default CPU to wake up by GPC */ + cd->cpu2wakeup = GPC_IMR1_CORE0; + + gpcv2_irq_instance = cd; + + register_syscore_ops(&imx_gpcv2_syscore_ops); + + return 0; +} + + +IRQCHIP_DECLARE(imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init); + + diff --git a/include/soc/imx/gpcv2.h b/include/soc/imx/gpcv2.h new file mode 100644 index 0000000..7234928 --- /dev/null +++ b/include/soc/imx/gpcv2.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __SOC_IMX_GPCV2_H__ +#define __SOC_IMX_GPCV2_H__ + +#define IMR_NUM 4 + +struct imx_gpcv2_irq { + struct raw_spinlock rlock; + void __iomem *gpc_base; + u32 wakeup_sources[IMR_NUM]; + u32 enabled_irqs[IMR_NUM]; + u32 cpu2wakeup; +}; + +void ca7_cpu_resume(void); +void imx7_suspend(void __iomem *ocram_vbase); + +#endif /* __SOC_IMX_GPCV2_H__ */