From patchwork Tue Jul 28 03:38:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?RWRkaWUgSHVhbmcgKOm7g+aZuuWCkSk=?= X-Patchwork-Id: 6879351 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 93667C05AC for ; Tue, 28 Jul 2015 03:41:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B8FC7206AC for ; Tue, 28 Jul 2015 03:41:14 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DAC882065B for ; Tue, 28 Jul 2015 03:41:13 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZJvjU-0007i4-5d; Tue, 28 Jul 2015 03:39:12 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZJvjO-0007gJ-VE; Tue, 28 Jul 2015 03:39:09 +0000 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 909926180; Tue, 28 Jul 2015 11:38:15 +0800 Received: from mtkslt208.mediatek.inc (10.21.15.95) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Tue, 28 Jul 2015 11:38:14 +0800 From: Eddie Huang To: Wolfram Sang Subject: [PATCH] i2c: mediatek: fix transfer error handling Date: Tue, 28 Jul 2015 11:38:05 +0800 Message-ID: <1438054685-25214-1-git-send-email-eddie.huang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150727_203907_233286_65F1F95B X-CRM114-Status: GOOD ( 16.19 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xudong Chen , srv_heupstream@mediatek.com, Sascha Hauer , Liguo Zhang , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-i2c@vger.kernel.org, Matthias Brugger , Eddie Huang , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Liguo Zhang Reset i2c dma engine in hw init function. When occur i2c ack error, mtk_i2c_irq may is twice, first is the ack error interrupt, then the complete interrupt, so i2c->irq_stat need keep the two interrupt value, and only call complete() for the complete interrupt. Signed-off-by: Liguo Zhang Signed-off-by: Eddie Huang --- drivers/i2c/busses/i2c-mt65xx.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index 9920eef..57d11b7 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -59,6 +59,7 @@ #define I2C_DMA_START_EN 0x0001 #define I2C_DMA_INT_FLAG_NONE 0x0000 #define I2C_DMA_CLR_FLAG 0x0000 +#define I2C_DMA_HARD_RST 0x0002 #define I2C_DEFAULT_SPEED 100000 /* hz */ #define MAX_FS_MODE_SPEED 400000 @@ -81,6 +82,7 @@ enum DMA_REGS_OFFSET { OFFSET_INT_FLAG = 0x0, OFFSET_INT_EN = 0x04, OFFSET_EN = 0x08, + OFFSET_RST = 0x0c, OFFSET_CON = 0x18, OFFSET_TX_MEM_ADDR = 0x1c, OFFSET_RX_MEM_ADDR = 0x20, @@ -262,6 +264,10 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c) I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN; writew(control_reg, i2c->base + OFFSET_CONTROL); writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN); + + writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST); + udelay(50); + writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST); } /* @@ -550,16 +556,20 @@ err_exit: static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id) { struct mtk_i2c *i2c = dev_id; - u16 restart_flag = 0; + u16 intr_stat = 0; - if (i2c->dev_comp->auto_restart) - restart_flag = I2C_RS_TRANSFER; + intr_stat = readw(i2c->base + OFFSET_INTR_STAT); + writew(intr_stat, i2c->base + OFFSET_INTR_STAT); - i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT); - writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR - | I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT); + /* + * when occurs i2c ack error, mtk_i2c_irq is called twice, + * first is the ack error interrupt, then the complete interrupt, + * i2c->irq_stat need keep the two interrupt value. + */ + i2c->irq_stat |= intr_stat; - complete(&i2c->msg_complete); + if (i2c->irq_stat & I2C_TRANSAC_COMP) + complete(&i2c->msg_complete); return IRQ_HANDLED; } @@ -729,3 +739,4 @@ module_platform_driver(mtk_i2c_driver); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("MediaTek I2C Bus Driver"); MODULE_AUTHOR("Xudong Chen "); +MODULE_AUTHOR("Liguo Zhang ");