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vger.kernel.org; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11FD041.mail.protection.outlook.com (10.173.161.137) with Microsoft SMTP Server (TLS) id 15.1.231.11 via Frontend Transport; Tue, 28 Jul 2015 09:56:29 +0000 Received: from b51421-server.ap.freescale.net (b51421-server.ap.freescale.net [10.193.102.57]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t6S9tYph013952; Tue, 28 Jul 2015 02:56:21 -0700 From: Haibo Chen To: , , , , , , , , Subject: [PATCH v2 5/5] ARM: dts: imx6ul-14x14-evk.dts: add tsc support Date: Tue, 28 Jul 2015 17:58:41 +0800 Message-ID: <1438077521-12857-6-git-send-email-haibo.chen@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1438077521-12857-1-git-send-email-haibo.chen@freescale.com> References: <1438077521-12857-1-git-send-email-haibo.chen@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; 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Signed-off-by: Haibo Chen --- arch/arm/boot/dts/imx6ul-14x14-evk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index 61b41ee..9995656 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -44,6 +44,15 @@ soc-supply = <®_soc>; }; +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 0>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -212,6 +221,15 @@ >; }; + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1