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freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BY2FFO11OLC007.mail.protection.outlook.com (10.1.14.254) with Microsoft SMTP Server (TLS) id 15.1.231.11 via Frontend Transport; Tue, 28 Jul 2015 14:43:22 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t6SEh4RA000941; Tue, 28 Jul 2015 07:43:18 -0700 From: Dong Aisheng To: Subject: [PATCH 4/4] clk: imx7d: only enable minimum required clocks Date: Tue, 28 Jul 2015 21:33:11 +0800 Message-ID: <1438090391-30329-5-git-send-email-aisheng.dong@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1438090391-30329-1-git-send-email-aisheng.dong@freescale.com> References: <1438090391-30329-1-git-send-email-aisheng.dong@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; 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SN1PR0301MB1645; 5:xdyRLjkmjeEgxwyILTTwtn/XzeNkVrrDKO8VbjSqm7Yt2evpIE7EqbKx4WKT2+vr29ytEX5mVTEtWtdpRDE/2QBFgbqCionirCPuGQ3+ONPfqMx/hmfddNgRUV5CtF07LS9ceJikiK833mOhrb3VOw==; 24:SBtAMZLoGmWZ/FAIeygvfja73qmlarlupNHEZ0BZiymml00J1m0Yu7pXl8nqn+A+W0xSxepXqclWpV+Yj+41PThMpeuFNRHVW64d1suXIes=; 20:NGLU3vvDk6c8wcFQ6iN7Qqa2jk96Q6UKY8E6v9USdDkn/W0wlo6fo5ldXqR0vm+5OGaOJfKmSlsyYBr9wDG0eA== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Jul 2015 14:43:22.8276 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR0301MB1645 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150728_104345_757231_B3B7A017 X-CRM114-Status: GOOD ( 17.03 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ranjani.Vaidyanathan@freescale.com, b20596@freescale.com, mturquette@baylibre.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, r64343@freescale.com, b20788@freescale.com, shawn.guo@linaro.org, b29396@freescale.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Formerly clk core does not support imx7d clock type well that all its clock operations requires the parent clock on. Therefore we enabled all clocks by default in clock driver initialization for other module clocks operate well. After patch 'clk: imx7d: using api with flag CLK_OPS_PARENT_ON', clk core can handle such clock type well, so we don't have to enable them all by default anymore. Instead, we only enable a minimum required set of clocks. BTW, clk_set_parent of plls clocks are also moved behind clks_init_on that every clock operation should happen after the minimum clocks are already enabled. Signed-off-by: Dong Aisheng --- drivers/clk/imx/clk-imx7d.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 8b0b023..dc54622 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -361,6 +361,14 @@ static const char *pll_enet_bypass_sel[] = { "pll_enet_main", "pll_enet_main_src static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", }; static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", }; +static int const clks_init_on[] __initconst = { + IMX7D_ARM_A7_ROOT_CLK, IMX7D_MAIN_AXI_ROOT_CLK, + IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK, + IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK, + IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK, + IMX7D_AHB_CHANNEL_ROOT_CLK, +}; + static struct clk_onecell_data clk_data; static void __init imx7d_clocks_init(struct device_node *ccm_node) @@ -830,14 +838,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - /* TO BE FIXED LATER - * Enable all clock to bring up imx7, otherwise system will be halt and block - * the other part upstream Because imx7d clock design changed, clock framework - * need do a little modify. - * Dong Aisheng is working on this. After that, this part need be changed. - */ - for (i = 0; i < IMX7D_CLK_END; i++) - clk_prepare_enable(clks[i]); + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + clk_prepare_enable(clks[clks_init_on[i]]); /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */ clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);