From patchwork Wed Jul 29 09:03:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Chen X-Patchwork-Id: 6890981 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 359AFC05AC for ; Wed, 29 Jul 2015 09:03:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 27318207D9 for ; Wed, 29 Jul 2015 09:03:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1A5B9207D8 for ; Wed, 29 Jul 2015 09:03:51 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZKNFG-0002kc-Au; Wed, 29 Jul 2015 09:01:50 +0000 Received: from mail-by2on0758.outbound.protection.outlook.com ([2a01:111:f400:fc0c::758] helo=na01-by2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZKNF0-0002V9-3l for linux-arm-kernel@lists.infradead.org; Wed, 29 Jul 2015 09:01:37 +0000 Received: from BY1PR03MB1386.namprd03.prod.outlook.com (10.162.127.140) by BY1PR03MB1452.namprd03.prod.outlook.com (10.162.127.158) with Microsoft SMTP Server (TLS) id 15.1.225.19; Wed, 29 Jul 2015 09:01:12 +0000 Received: from CH1PR03CA007.namprd03.prod.outlook.com (10.255.156.152) by BY1PR03MB1386.namprd03.prod.outlook.com (10.162.127.140) with Microsoft SMTP Server (TLS) id 15.1.225.19; Wed, 29 Jul 2015 09:01:11 +0000 Received: from BN1AFFO11FD008.protection.gbl (10.255.156.132) by CH1PR03CA007.outlook.office365.com (10.255.156.152) with Microsoft SMTP Server (TLS) id 15.1.201.16 via Frontend Transport; Wed, 29 Jul 2015 09:01:11 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=freescale.com; vger.kernel.org; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BN1AFFO11FD008.mail.protection.outlook.com (10.58.52.68) with Microsoft SMTP Server (TLS) id 15.1.231.11 via Frontend Transport; Wed, 29 Jul 2015 09:01:11 +0000 Received: from b51421-server.ap.freescale.net (b51421-server.ap.freescale.net [10.193.102.57]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id t6T90uDs011542; Wed, 29 Jul 2015 02:01:05 -0700 From: Haibo Chen To: , , , , , , , , , Subject: [PATCH v3 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400 Date: Wed, 29 Jul 2015 17:03:52 +0800 Message-ID: <1438160637-28061-2-git-send-email-haibo.chen@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1438160637-28061-1-git-send-email-haibo.chen@freescale.com> References: <1438160637-28061-1-git-send-email-haibo.chen@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BN1AFFO11FD008; 1:+w62w/Hg6InRe8W3T3J5v1iwtji1N3i8PPjz/fz8dpyPav52q1X0/D2VfcuebdKSewW8i/6lALlrDTbEBzbyIk4F9rEhINwKZRzcRQ8GHmKPKSmMQWT/i7YbqkEc4UAQ+ho37L4aW8Idbp7ICFDAXuuUJH8t1OuEV0vH5UN45XdWhMrx7Eb5EHentIoTMtQZ67HEz3XBnOr+T4q22Xj//QNa2eCiSEobn7Ge6DwJLmI0wGbKRcgSyVg3jmN0bBrhbmww8cyC501/ehtOSrFBJoMWypeuaY6jg/ixal4Q7mEw4/5a/wAC4tvOOrwcACt2MhFWwaeGJz+ujiHhmfltSg== X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(2980300002)(339900001)(189002)(199003)(86362001)(19580405001)(47776003)(2950100001)(4001450100002)(36756003)(189998001)(33646002)(104016003)(77096005)(230783001)(229853001)(106466001)(85426001)(6806004)(48376002)(76176999)(62966003)(46102003)(77156002)(87936001)(19580395003)(2201001)(5001960100002)(92566002)(105606002)(50986999)(921003)(1121003); DIR:OUT; SFP:1102; SCL:1; SRVR:BY1PR03MB1386; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Exchange-Diagnostics: 1; BY1PR03MB1386; 2:oyuEFgulS+lljvaA66xysjBqQF3uqzDOqvlEhZ+lFFFu9l9svrIdf3LaPFV9W5OYY2OgWdw+vUSSqVbwv9TcE6L9o8aECCQpiyvcbOYgUS/YxbJqeZXo9Lx5iaY77kuJpNzg2wc4nNbjFlWobGSaLPiaLJrroYgbF1X1QGht88Q=; 3:twIJxRvnfjAYYgipG2Ho4hAkmVF0JgQ29VYsEuYHTpqfA+85N3yk/Eqccdk44gCwDkl8nwUvXyuOJg6gba2RqUqsI5AwtRGsLNBOxV8hhUcGzlOX53HfCIGPcvfrywNPyaSOgwP9DbY2wTcDjqPC2DEGvOBnrXUnxKm/xbbPaGgFEK0kSpz9uZPYme4K8owF3fp3Gw4+oiMwF5Y/BIHDqi/qc+sq/1URsQExXni1Yug=; 25:yqQVAX5r/8leDPLyciVroMTwhabKaE0oqm6ady409wOLFfNjukOajhKOgpK3UsXPHTaO/J18D8iMUJQoqdDwnlH7jLohM2fv5dzzmmY4n+Pv8qnKsXtsHXL/fPKctBAB3PAHjVHnPw761NpO2pS1xAOqtbWsV9AMQlZKs8xi3RdjQBCOYN0g9Cj4Dmg07vJc4j1OdbZKoBOy73VmXAMJV+jlAVW0+5hw0C7G/tAMS8WaNRXkl90SA6rKqlbVtUvGZ8GA6AykxLKffMoLlpKyIw== X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:; SRVR:BY1PR03MB1386; UriScan:; BCL:0; PCL:0; RULEID:; SRVR:BY1PR03MB1452; X-Microsoft-Exchange-Diagnostics: 1; BY1PR03MB1386; 20:42qK0Oy9cu/r3+H4rQ0UZzmfOEVQ6F2IbVOvWYnRMiNvA5kbXh/iKdfurxCqQEdxI2CNtRXK57+WMTj9AhvQo5r5WfIeBHcW+3iPGid0b+PVqWyf4uK4acC0pzjVgITa6nLM6p9Js/YYSvIf7ZohOSmzOkjEYa9A3ya4ZgX7luSUsP32I+ZpGvqvZ/3TzqICWuALMXprAsq06gd12pUJlOJXMLvcxxRma244s3qdZQfSmhUbPjbKgj+fdN3v+TIWl9dYqXkdz8U1BKEdRhhdxuxA/UWZmk5k+X/q0pMEdRJBVUkaNhUIca7cD9KWIV0uO/jbfpq8beCu9ave7KEMz66oKl6Pq10F46dpeVHKKV8=; 4:ahT3lHNZcSvBT1wqFIunwjv9CYQVfofuxMubgpH1IgFhhloxLdDonpegnMqKsj/8IZDZCAtn7V9lFQF3e0AIJmNntdXq1QnjhmSq34eW46JTv5Xbb5zaMGLv3oII51lh1Dj44H3e7rA2+7wOyjuYru4krDKnpCCDnDei0rbc/eeqFHr54jWEKhfkcl7kKLxZMKqgCkaXll6+fufjmP2DuU1rD6sjTwL2ye7jb+Q6N+92WGWGlsnD3sREVpgb3OUVJEPMa9LIKKprEbGQpBMsviSmiVesaVO37AykXy2tQA4= BY1PR03MB1386: X-MS-Exchange-Organization-RulesExecuted X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:BY1PR03MB1386; BCL:0; PCL:0; RULEID:; SRVR:BY1PR03MB1386; X-Forefront-PRVS: 0652EA5565 X-Microsoft-Exchange-Diagnostics: 1; BY1PR03MB1386; 23:A83H553IP1oNewde13ZYShiEZJjUcTXFRC0DyuTsBYiwPIL6pkQnbp3tqdN0jnsTUOb1pu7yeLJMZJklgqdEwKntHip9blE/tNedc18FK6Jok544N1oxR7KeVI9e9eckpmMRnH+qClJ8+gyh1dj6UmB9YILrfKu9Vvw8Zu2Xz7/8UcrJYUFQZbfUtDbawaI3Jy8ISEy92Tj22uKuSqDqfLIq5E3OSslXevtYT0q1io2eZY/MUJREsUgcWcjlnNzJxk99C24htvBiNmV6NI31vZqTgRKkXiX1JqCRJt2nk9u4T1i7yxJu1jXUNkx2d4N6MR2UoZ1kjrRHEFjrh8/n/N4Bac6nGP80sBKrxiE+usgdRdwnuaehinKa5EAvZ7HOhsORs5e3hMAKRo0rOreJPrH9ked7wB/4aZzWU2gDSIKnRenYMXzT+xbM1GXIf0bIaXVmmbc2x12u/wsjFFUVajvOd5FBecoe708+cydK5p1qoRMEwM466EGmu1gDoezIy3uKZkk/d6rK4lWbpmy3hDNeLOQzJyyZ0fFHLLReSPjBNplvz7W61qjlUcvxi+ztpykCHC+vk/WxfthtQV0ByD5h+qXNLyr0aY+/hUrDQkghmjSAkca0XWY4tW9H74tIARpd0sP+FB2IVckJ2aORmXlQbYp+XICyYFia1aHiJici8uwOrechMstMKoJlgwZTbynK17F48gvEDGauG36EUB9mHHFO+wN4jIEiiD44bhVo2uUBUDsETRWbaCzmVvI79EqKVqJPtBzEbOvtOMUOknEnd8lqn6z2SWDvgx7un2sgtpEW6uIzVyRaTbxJbCCn6SizVK0PBW0bTNku+7MpaHccVt+YY1pC8TUxV3rItu0IcpTvs/YOAf1n8UlFDYX4Dh0GLJZ3smoKIXUdsOHGCQ== X-Microsoft-Exchange-Diagnostics: 1; BY1PR03MB1386; 5:eUl+S2zTPMAf9gzuRr7Lrlw76N3c7WeVFMdr5XDhCwbagoyhk+YVcameAcWHyBrm65Z6TFfeaVkotJvZVS3AaJ4z2AEjV9xmBjn37kQ4tnUcT1hf1r3H8kGLCorhSWjgc0G/DwVCdFj/0UHF8QlRHQ==; 24:V9rTAhiOE9g3BaNenMvK14oM53fcgM9SuIPk+cCv3R93p5yboupmIV6wKiTy/JQpD7pNn1pxWsBoKo3ZTK5hISDq8aJlsvlzSjjRmVqssJA=; 20:/VhbV+YIBdiUio/4WIRfjBS4KgCW4ltK4Xi0W8lbWN2iFXF6pwUVJDOU4BPKF/BEc0Pvyoh1C3M/x/X37qOWsQ== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jul 2015 09:01:11.4739 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR03MB1386 X-Microsoft-Exchange-Diagnostics: 1; BY1PR03MB1452; 2:bLAHyKyRHTJbM7pccZZ/K2nE/omygnYUSrCRln/JAoocAUXau7nlau/GQZfnN2abYib3AEBIYE+7PI8ThEv6VYDm7UaClweaZd/wqjU/S+HaYemlERY2271mnLQ8Jw4aMaNYiRgoIHhJX6a78lBrNES3uNc52UJRJbPx1plHslU=; 3:aZHoaHa5KzaD5JANnvZuSRQnsFJQ8de3oqqIswqY3JyXsxqIHrAZF9T2PI812rnV2WnMTnQk3d6ZlHbh08pXcGT+yD3nrUlRdhlcVEm9g0sDImzU42vCvlRzv9eaXOHr/1COI4ReH/S8+GtNt7+ZulOhX7Dlw0QR2+w8fy+6fQmoz6KUI6YnrG6vHw82QOmSlUnUDtmsRuO7DSn2m1iZfkPQ0QkEZt5td4X/8gn/hqo=; 25:mbdB1ab9ODsLoNmUQ8gnmU2UdDLLMHRHsQ+GLq1ShwDEcc36CAyZiVPMcVyb99aL6JeLIjkbPjKZVbcjpWnPWaSVs9knHId6ZFkp0QiJJWta+RB9XK/AZoOzXFP6Bb3RLxr9X92KlLW2LCIBJN4mllZVJmg/oZfpT9EtiRw/lQoOzH7Mwcq+c+3kJafRn5AwRIX4vKZ83iR+NR26eaa1HQJsFUL8qbsDG50k7V1AT4GXpXm3H7suy5DpliSFGj+hT2/OAMjg41I0+FHVqeO4bA==; 23:1eZsMLaYTDXROSk4wm+DTHtLE6qQNHlhDvPnygS1Eww9WhRDJkzwIc2F5h01Abd/Fg3evAfHxzYiuz+ErSTbFbYP36Fg/H8LzSYtVpCD7SAITTy/KRtkIs+nD/l6t9x49VMxHuPgswWoSeO9SxowvSt7Yu5GMqeR+4AvOeNmPdEuhzYhXFubRIwMGe4jh6FW8d0CvG4PCJTlDSItedUbE7r7HkEDqnIqEwRRzO7jCg/DUg8eak5wvMcF3N+4LQf4 X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150729_020134_376789_077534EA X-CRM114-Status: GOOD ( 23.63 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fabio.estevam@freescale.com, devicetree@vger.kernel.org, haibo.chen@freescale.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johan.derycke@barco.com, b29396@freescale.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The imx7d usdhc is derived from imx6sx, the difference is that imx7d support HS400. So introduce a new compatible string for imx7d and add HS400 support for imx7d usdhc. Signed-off-by: Haibo Chen --- drivers/mmc/host/sdhci-esdhc-imx.c | 66 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index c6b9f64..b441eed 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -44,6 +44,7 @@ #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) +#define ESDHC_MIX_CTRL_HS400_EN (1 << 26) /* Bits 3 and 6 are not SDHCI standard definitions */ #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 /* Tuning bits */ @@ -60,6 +61,16 @@ #define ESDHC_TUNE_CTRL_MIN 0 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) +/* strobe dll register */ +#define ESDHC_STROBE_DLL_CTRL 0x70 +#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) +#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) +#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 + +#define ESDHC_STROBE_DLL_STATUS 0x74 +#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) +#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 + #define ESDHC_TUNING_CTRL 0xcc #define ESDHC_STD_TUNING_EN (1 << 24) /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ @@ -120,6 +131,8 @@ #define ESDHC_FLAG_ERR004536 BIT(7) /* The IP supports HS200 mode */ #define ESDHC_FLAG_HS200 BIT(8) +/* The IP supports HS400 mode */ +#define ESDHC_FLAG_SUP_HS400 BIT(9) struct esdhc_soc_data { u32 flags; @@ -156,6 +169,12 @@ static struct esdhc_soc_data usdhc_imx6sx_data = { | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, }; +static struct esdhc_soc_data usdhc_imx7d_data = { + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 + | ESDHC_FLAG_SUP_HS400, +}; + struct pltfm_imx_data { u32 scratchpad; struct pinctrl *pinctrl; @@ -199,6 +218,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = { { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, + { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); @@ -274,6 +294,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING; + + /* imx7d does not have a support_hs400 register, fake one */ + if (imx_data->socdata->flags & ESDHC_FLAG_SUP_HS400) + val |= SDHCI_SUPPORT_HS400; } } @@ -774,6 +798,7 @@ static int esdhc_change_pinstate(struct sdhci_host *host, break; case MMC_TIMING_UHS_SDR104: case MMC_TIMING_MMC_HS200: + case MMC_TIMING_MMC_HS400: pinctrl = imx_data->pins_200mhz; break; default: @@ -784,6 +809,30 @@ static int esdhc_change_pinstate(struct sdhci_host *host, return pinctrl_select_state(imx_data->pinctrl, pinctrl); } +static void esdhc_set_strobe_dll(struct sdhci_host *host) +{ + u32 v; + + /* force a reset on strobe dll */ + writel(ESDHC_STROBE_DLL_CTRL_RESET, host->ioaddr + ESDHC_STROBE_DLL_CTRL); + /* + * enable strobe dll ctrl and adjust the delay target + * for the uSDHC loopback read clock + */ + v = ESDHC_STROBE_DLL_CTRL_ENABLE | + (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); + writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); + /* wait 1us to make sure strobe dll status register stable */ + udelay(1); + v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); + if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) + dev_warn(mmc_dev(host->mmc), + "warning! HS400 strobe DLL status REF not lock!\n"); + if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) + dev_warn(mmc_dev(host->mmc), + "warning! HS400 strobe DLL status SLV not lock!\n"); +} + static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); @@ -795,7 +844,13 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) case MMC_TIMING_UHS_SDR25: case MMC_TIMING_UHS_SDR50: case MMC_TIMING_UHS_SDR104: + break; case MMC_TIMING_MMC_HS200: + /* disable ddr mode and disable HS400 mode */ + writel(readl(host->ioaddr + ESDHC_MIX_CTRL) & + ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN), + host->ioaddr + ESDHC_MIX_CTRL); + imx_data->is_ddr = 0; break; case MMC_TIMING_UHS_DDR50: case MMC_TIMING_MMC_DDR52: @@ -813,6 +868,14 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) writel(v, host->ioaddr + ESDHC_DLL_CTRL); } break; + case MMC_TIMING_MMC_HS400: + writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | + ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN, + host->ioaddr + ESDHC_MIX_CTRL); + imx_data->is_ddr = 1; + if (host->clock == 200000000) + esdhc_set_strobe_dll(host); + break; } esdhc_change_pinstate(host, timing); @@ -1100,6 +1163,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; + if (imx_data->socdata->flags & ESDHC_FLAG_SUP_HS400) + host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; + if (of_id) err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); else