From patchwork Mon Aug 10 08:18:03 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haibo Chen X-Patchwork-Id: 6980661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3B5799F39D for ; Mon, 10 Aug 2015 08:18:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1FFF520610 for ; Mon, 10 Aug 2015 08:18:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0E3052060F for ; Mon, 10 Aug 2015 08:18:54 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZOiFz-0007PE-82; Mon, 10 Aug 2015 08:16:31 +0000 Received: from mail-bn1bon0141.outbound.protection.outlook.com ([157.56.111.141] helo=na01-bn1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZOiFs-0007Ji-55 for linux-arm-kernel@lists.infradead.org; Mon, 10 Aug 2015 08:16:26 +0000 Received: from BLUPR0301CA0039.namprd03.prod.outlook.com (10.162.113.177) by CY1PR03MB1423.namprd03.prod.outlook.com (10.163.17.145) with Microsoft SMTP Server (TLS) id 15.1.225.19; Mon, 10 Aug 2015 08:16:01 +0000 Received: from BN1AFFO11OLC003.protection.gbl (2a01:111:f400:7c10::164) by BLUPR0301CA0039.outlook.office365.com (2a01:111:e400:5259::49) with Microsoft SMTP Server (TLS) id 15.1.225.19 via Frontend Transport; Mon, 10 Aug 2015 08:16:01 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; vger.kernel.org; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11OLC003.mail.protection.outlook.com (10.58.53.74) with Microsoft SMTP Server (TLS) id 15.1.243.9 via Frontend Transport; Mon, 10 Aug 2015 08:16:00 +0000 Received: from b51421-server.ap.freescale.net (b51421-server.ap.freescale.net [10.193.102.57]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t7A8FmJi017011; Mon, 10 Aug 2015 01:15:55 -0700 From: Haibo Chen To: , , , , , , , , , Subject: [PATCH v5 1/6] mmc: sdhci-esdhc-imx: add imx7d support and support HS400 Date: Mon, 10 Aug 2015 16:18:03 +0800 Message-ID: <1439194688-18335-2-git-send-email-haibo.chen@freescale.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1439194688-18335-1-git-send-email-haibo.chen@freescale.com> References: <1439194688-18335-1-git-send-email-haibo.chen@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BN1AFFO11OLC003; 1:qRv8kSjKbBARN3ohrOrwlKHaOvqiazopBUvd4OgCYZv4AYS+IQUiM5oZBRYxGLFQ3iKVhJV/xXUpN7LHcu+6J479yblp9gXr1U01fsGizsG5gt4dk+WjxBARMchxsYR8HykTaQXRsDM/biX7gBGxhk8SBIEPkQlYDHCPgsIKFUVsOQ3xJUJ9HjD2ahIRFuVV7QDhu3qnmK185KM3ZLK0xSNZ2O3JoMcvPojMsXEW7K3qjWj0sb1JaASqP8y0MPn/is83E46mklIhcwt/+UKgcKF4N5S6ZpCGEktc+5yCg3UhBu59v8TFw6uO8vls4+843ocqkh6vV7+CWAhts7/7IQ== X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(2980300002)(339900001)(189002)(199003)(46102003)(33646002)(86362001)(104016003)(19580405001)(77096005)(68736005)(6806004)(5003940100001)(69596002)(77156002)(62966003)(85426001)(87936001)(50226001)(19580395003)(229853001)(2201001)(2950100001)(230783001)(47776003)(36756003)(5001960100002)(5001920100001)(189998001)(92566002)(50466002)(50986999)(5001830100001)(4001450100002)(48376002)(76176999)(64706001)(4001540100001)(81156007)(97736004)(5001860100001)(5001770100001)(106466001)(105606002)(921003)(1121003); DIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR03MB1423; H:az84smr01.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Exchange-Diagnostics: 1; CY1PR03MB1423; 2:rAVpLYrh2esEKoU5ylErhrGC3v3dqbjq6QQfugcmuGDwfEICEzyeJ0c3DHovxZAsWugV3ETUpGQrHWbSeQ2D5tjd+0VFmT4/c/BSpN26kCDupTYKT7B0yAf/PAhSHrePW2YlHIsHvQXkfIDE6jDFpWaHsO1GL2C4VziO0YYWPuU=; 3:Xd8edczRA6JAB9ayzcdRz2YpLafRVveSwgMaZ9bD8ulmeimm1dWpuBEYcVZyL+iW2/h82qV7sZJztt12GsfA06uR7OohAR5SjgxUW5KDJTriQ3zgcQi0LfmiuwO2baQLvKw66o+utgi1MYfmGC7zvZ9ymoZooGLqxyl7uhOgdR23FEsNsnZ4SNZIA/yXqCBPmUtS4BeI4bRilLbx6kTn2G4f/DmChfv3KXOUiMz0aRQ=; 25:BjXuBTaHVoQdKU7GYA5vo0WyrWUKonNchLbEb80QZF+slBMQsUkynVlFZAJf7dW/4ln4AQ84J64JB1dNOYFuqCASyMMm/N8XmTmmf4vZWPI/N1aDYL4CTNZql4wIbFjnhdi1EfxK2kZVKpmO5L0PeMcajN3K1HPzutZuFzSoEHh7LycmnHETv0RzTM/yBQDxkbp7ymEABUGx1ykJObZU7ohczTc59MmOsWSvyccRECpiXmAh7QeyI5RuMaT0nY9K8kFCM9MZFDfQRP8wpYIZ7g== X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR03MB1423; X-Microsoft-Exchange-Diagnostics: 1; CY1PR03MB1423; 20:qEpGr4/Ku/KNcpS0IGRHC1/1n31aDTn9M5XM7IpOUcqv0GHU9smluRza8DOZ6kuGDTM6j4m0sDXmk+pHPj12fvx6k+aerC/8Naxq15fB+zFv/Nf2WHR5YsmvNtciRAO6hpFubDGkUzFYd2y1DQkuwX8KGGoJDtzrXQndCRoBGvWBzsUKi/AArgdsfCNHUARxjivVIcKKeEnNU2qedrfkqVZRXdZEOyDKHS/AIOaA44qcDXbL6Ksm/3EzRjYaL8yMp3Y7Jv8x3YnHbIPZol5hUnU4OU1wSDOMZLB7JqcjYs0x3A46TuIQyAwBl2RZ0uWyQ4L+gXTOQaSbS2mZkEBd8RhBsazQc4j+Gb76nIZCrJg=; 4:kF7fVJWDtL9sylLMOmgZM3k3BvGTIwutkSJfkc9KaURDUOJknhmM+l4CjZmx1BoI0+YHlvWc1Tg8orS/pxI/iHd3Unma4pUjUxVBUrArxI2XmteGPnJQfZapTjwZWzHEX9VLZRevDmKTAUWvkc9PgTXe45pEnwkm8nyLgWFC3QNwX+apUAF2ujneKGDpnOhUEDhbzPH8mqR3LBgt671rl+NlgX4GF37fSTMr3w4jQ5oZbA2m3OrWO1GeU2vhW86taH0edlhWDeLKIua7lPaORkssRd/bs/GeObgvnBeFasQ= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:CY1PR03MB1423; BCL:0; PCL:0; RULEID:; SRVR:CY1PR03MB1423; X-Forefront-PRVS: 06640999CA X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY1PR03MB1423; 23:esT/NDh3KtYla6tuudFeM+Fw/vp0+eaMMKxqSoR4g?= =?us-ascii?Q?VDkOQAq+ggbGubwegWax7jNd7WrwQIwcWT4akY8nSazLSaYnI3rEzIWkmIKS?= =?us-ascii?Q?qw0EvQK2wD47gdPfE88zokx2k8czF7zgvSU9eEZ+fla/uxkCz/Arm9zYgM+J?= =?us-ascii?Q?a5uaVpf96MgReHx+fWlODj0k0q4ru0t5F1oLfW0afqEKPP4xNRm+yYZVRzWQ?= =?us-ascii?Q?lS1CLljoM+366QM1zmKl0Lul1UEB9weF2nwxnbUQd6cloFdIueUzM59d7jqA?= =?us-ascii?Q?4cUpakU6voc2ssTbkPBmnnJtUHwyU8MleG8C9WmehC0dyOixTbfFFwgiABIn?= =?us-ascii?Q?y9HIqXZU55j65OdO9cFMu97Ta0ZxIyTXdKEY2756PcjDSCcxbwl31FjXqhQQ?= =?us-ascii?Q?oJISc3pX80Wm5C0Ge4vDyu/2EdwSNWh2jfzVSUiKyc1Iz6ACsMldzOGy2SEi?= =?us-ascii?Q?Aa36hM82QpdZv5NWT8+OCGoLuAX1l8wjRplUxZ/LwnfA8AN+PgBqt8SJJrkD?= =?us-ascii?Q?KPXYOqObkA3uEh4s3ys0Fn0ZRANfjlRlDKzl8Xz/zR4Mk+w9eVT4cH6jIaOR?= =?us-ascii?Q?G+VqNMgPFGzF+K9hXkuNDj1Y5GNJks6nlueQPXFuLTq5x7i45/wbJGm4FIRX?= =?us-ascii?Q?bmLXtOfgB2CIzPR7/SK6HF222De6ynOw15ZCEf1F8GBT25BGBc82F/nTF+Y4?= =?us-ascii?Q?ZAn4gA7c6nGHG6GxDPRy096GhyjxkCw0sPdu/0OlY/pKa1585jyyWoqMSb+4?= =?us-ascii?Q?BieVxFVDZ7AYrmxpAPArr5U9gLiZBtKrH2HVDucYRbj67tCESu0G78/nAJ28?= =?us-ascii?Q?lJq6llJVjBCjM7rMcMj9D2aUfgbM+2NY1VylNDU+2xMw92s/o+rC6y5gp24e?= =?us-ascii?Q?ir1LZ4gxaSGM9R2z4ie4RWx6v2IGyP241FbtYnhkgWQBgr47yI0oidqfCkTl?= =?us-ascii?Q?rwqznl/L3gIf2exH1MIZFpgG8E4Y1AepE3Ps43buuM6dRfgpEHmNVIGXStRW?= =?us-ascii?Q?EHbMiUgk3RSidu3XgABTz8a8jnKaMr64WloZ17L5TPBwMQDyHhEVbtPhRxV+?= =?us-ascii?Q?PXdCmmInRYHdcjQma+avysOPZ5ts54gFru9/AibnKr83rgVC+TUbeIiX0sdp?= =?us-ascii?Q?JbajYPBF31HnBnTKvTu+P8IGCv1EVw/iXsL9n82KoL4Fpmy1EoD4u/04NmKt?= =?us-ascii?Q?PFjqzYBW6YqRahlSq23bI1ggzFnBGG8omP/DylJzhdbmzy/3Wh+Vlv5li/nq?= =?us-ascii?Q?OzMzbgNt5eFUbPFJeE=3D?= X-Microsoft-Exchange-Diagnostics: 1; CY1PR03MB1423; 5:fxWukW2RA44SKk9EafEl5LkJZGHu1Z+7BJ+f08uOSbRTdTZOspP6HibRIA+B+DdtQXKc6v5ja2lEknPr0TbKGU+5LHQi2IaOZChuNAs+cMmWCa0cQ0ztdQSD9JXDTSv8P9VT8P4lKdPCVXtS/9VThw==; 24:tKSbpRz2murJwd5ivXxUnArXZwddQLfaA5Nsk5pmJ9OWF9CaeuaH5/DPljrlKR0WvJZMGX988Y2YrVHCZIgue+GFhvyz0J+FzlPKglxygB8=; 20:Hbjq1XNMIFsvyd2yvxS7dK7yBzHE1LusnE7U3Cpp1O/sIr0EMhocPvzRuvF8LMb7q1KAwfny1/8kqTvltxA21w== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2015 08:16:00.6158 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR03MB1423 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150810_011624_635921_A9E40389 X-CRM114-Status: GOOD ( 21.26 ) X-Spam-Score: -1.9 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fabio.estevam@freescale.com, devicetree@vger.kernel.org, haibo.chen@freescale.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, mkl@pengutronix.de, johan.derycke@barco.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAD_ENC_HEADER,BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The imx7d usdhc is derived from imx6sx, the difference is that imx7d support HS400. So introduce a new compatible string for imx7d and add HS400 support for imx7d usdhc. Signed-off-by: Haibo Chen --- drivers/mmc/host/sdhci-esdhc-imx.c | 88 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 85 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index c6b9f64..2a816ad 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -44,6 +44,7 @@ #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) +#define ESDHC_MIX_CTRL_HS400_EN (1 << 26) /* Bits 3 and 6 are not SDHCI standard definitions */ #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 /* Tuning bits */ @@ -60,6 +61,16 @@ #define ESDHC_TUNE_CTRL_MIN 0 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) +/* strobe dll register */ +#define ESDHC_STROBE_DLL_CTRL 0x70 +#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) +#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) +#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 + +#define ESDHC_STROBE_DLL_STATUS 0x74 +#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) +#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 + #define ESDHC_TUNING_CTRL 0xcc #define ESDHC_STD_TUNING_EN (1 << 24) /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ @@ -120,6 +131,11 @@ #define ESDHC_FLAG_ERR004536 BIT(7) /* The IP supports HS200 mode */ #define ESDHC_FLAG_HS200 BIT(8) +/* The IP supports HS400 mode */ +#define ESDHC_FLAG_HS400 BIT(9) + +/* A higher clock ferquency than this rate requires strobell dll control */ +#define ESDHC_STROBE_DLL_CLK_FREQ 100000000 struct esdhc_soc_data { u32 flags; @@ -156,6 +172,12 @@ static struct esdhc_soc_data usdhc_imx6sx_data = { | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, }; +static struct esdhc_soc_data usdhc_imx7d_data = { + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 + | ESDHC_FLAG_HS400, +}; + struct pltfm_imx_data { u32 scratchpad; struct pinctrl *pinctrl; @@ -199,6 +221,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = { { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, + { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); @@ -274,6 +297,9 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING; + + if (imx_data->socdata->flags & ESDHC_FLAG_HS400) + val |= SDHCI_SUPPORT_HS400; } } @@ -774,6 +800,7 @@ static int esdhc_change_pinstate(struct sdhci_host *host, break; case MMC_TIMING_UHS_SDR104: case MMC_TIMING_MMC_HS200: + case MMC_TIMING_MMC_HS400: pinctrl = imx_data->pins_200mhz; break; default: @@ -784,12 +811,57 @@ static int esdhc_change_pinstate(struct sdhci_host *host, return pinctrl_select_state(imx_data->pinctrl, pinctrl); } +/* + * For HS400 eMMC, there is a data_strobe line, this signal is generated + * by the device and used for data output and CRC status response output + * in HS400 mode. The frequency of this signal follows the frequency of + * CLK generated by host. Host receive the data which is aligned to the + * edge of data_strobe line. Due to the time delay between CLK line and + * data_strobe line, if the delay time is larger than one clock cycle, + * then CLK and data_strobe line will misaligned, read error shows up. + * So when the CLK is higher than 100MHz, each clock cycle is short enough, + * host should config the delay target. + */ +static void esdhc_set_strobe_dll(struct sdhci_host *host) +{ + u32 v; + + if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) { + /* force a reset on strobe dll */ + writel(ESDHC_STROBE_DLL_CTRL_RESET, + host->ioaddr + ESDHC_STROBE_DLL_CTRL); + /* + * enable strobe dll ctrl and adjust the delay target + * for the uSDHC loopback read clock + */ + v = ESDHC_STROBE_DLL_CTRL_ENABLE | + (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); + writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); + /* wait 1us to make sure strobe dll status register stable */ + udelay(1); + v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS); + if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK)) + dev_warn(mmc_dev(host->mmc), + "warning! HS400 strobe DLL status REF not lock!\n"); + if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK)) + dev_warn(mmc_dev(host->mmc), + "warning! HS400 strobe DLL status SLV not lock!\n"); + } +} + static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) { + u32 m; struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = pltfm_host->priv; struct esdhc_platform_data *boarddata = &imx_data->boarddata; + /* disable ddr mode and disable HS400 mode */ + m = readl(host->ioaddr + ESDHC_MIX_CTRL); + m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); + writel(m, host->ioaddr + ESDHC_MIX_CTRL); + imx_data->is_ddr = 0; + switch (timing) { case MMC_TIMING_UHS_SDR12: case MMC_TIMING_UHS_SDR25: @@ -799,9 +871,9 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) break; case MMC_TIMING_UHS_DDR50: case MMC_TIMING_MMC_DDR52: - writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | - ESDHC_MIX_CTRL_DDREN, - host->ioaddr + ESDHC_MIX_CTRL); + m = readl(host->ioaddr + ESDHC_MIX_CTRL); + m |= ESDHC_MIX_CTRL_DDREN; + writel(m, host->ioaddr + ESDHC_MIX_CTRL); imx_data->is_ddr = 1; if (boarddata->delay_line) { u32 v; @@ -813,6 +885,13 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) writel(v, host->ioaddr + ESDHC_DLL_CTRL); } break; + case MMC_TIMING_MMC_HS400: + m = readl(host->ioaddr + ESDHC_MIX_CTRL); + m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; + writel(m, host->ioaddr + ESDHC_MIX_CTRL); + imx_data->is_ddr = 1; + esdhc_set_strobe_dll(host); + break; } esdhc_change_pinstate(host, timing); @@ -1100,6 +1179,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; + if (imx_data->socdata->flags & ESDHC_FLAG_HS400) + host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; + if (of_id) err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); else