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But if the SDIO/SD/MMC I/O speed is fast enough, this default watermark level and burst length will be the performance bottleneck. For example, i.MX7D support eMMC HS400 mode, this mode can run in 8 bit, 200MHZ DDR mode. So the I/O speed improve a lot compare to SD3.0. The default burst length is 8, if we don't change this value, in HS400 mode, when we do eMMC read operation, we can find that the clock signal will stop for a period of time. This means the speed of data moving on AHB bus is slower than I/O speed. So we should improve the speed of data moving on AHB bus. This patch set the default burst length as 16, and set the default watermark level as 64. The test result is the clock signal has no stop during the eMMC HS400 operation. Signed-off-by: Haibo Chen --- drivers/mmc/host/sdhci-esdhc-imx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index d7ec993..1b31d36 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -1162,7 +1162,8 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev) * to something insane. Change it back here. */ if (esdhc_is_usdhc(imx_data)) { - writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); + writel(0x10401040, host->ioaddr + ESDHC_WTMK_LVL); + host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; host->mmc->caps |= MMC_CAP_1_8V_DDR;