From patchwork Tue Aug 11 17:03:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 6993601 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 25D4EC05AC for ; Tue, 11 Aug 2015 17:06:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2A3CC204D5 for ; Tue, 11 Aug 2015 17:06:12 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 43C6B20279 for ; Tue, 11 Aug 2015 17:06:11 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZPCyS-0002r8-7O; Tue, 11 Aug 2015 17:04:28 +0000 Received: from down.free-electrons.com ([37.187.137.238] helo=mail.free-electrons.com) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZPCyE-0002jN-7r for linux-arm-kernel@lists.infradead.org; Tue, 11 Aug 2015 17:04:15 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id 59F7C5C1; Tue, 11 Aug 2015 19:04:06 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (von69-1-88-162-9-206.fbx.proxad.net [88.162.9.206]) by mail.free-electrons.com (Postfix) with ESMTPSA id 09E8E36A; Tue, 11 Aug 2015 19:04:05 +0200 (CEST) From: Gregory CLEMENT To: Russell King Subject: [PATCH] ARM: mm: fix support for HW coherent systems in PL310 cache Date: Tue, 11 Aug 2015 19:03:35 +0200 Message-Id: <1439312615-6160-1-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 2.1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150811_100414_546663_DF94FB89 X-CRM114-Status: GOOD ( 14.82 ) X-Spam-Score: -2.8 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Petazzoni , Andrew Lunn , Jason Cooper , Tawfik Bayouk , Boris BREZILLON , Nadav Haklai , Lior Amsalem , Ezequiel Garcia , Gregory CLEMENT , Maxime Ripard , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Nadav Haklai When a PL310 cache is used in a system that provides hardware coherency, the entire outer cache operations are useless, and can be skipped. Moreover, on some systems, it is harmful as it causes deadlocks between the Marvell coherency mechanism, the Marvell PCIe controller and the Cortex-A9. This commit extends a previous commit: 98ea2dba65932ffc456b6d7b11b8a0624e2f7b95 which added the io-coherent support for the PL310 cache by also disabling the outer cache flush range operation. In the current kernel implementation, the outer cache flush range operation is triggered by the dma_alloc function. This operation can be take place during runtime and in some circumstances may lead to the PCIe/PL310 deadlock on Armada 375/38x SoCs. Signed-off-by: Nadav Haklai Reviewed-by: Ofer Heifetz Signed-off-by: Gregory CLEMENT --- arch/arm/mm/cache-l2x0.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 71b3d3309024..5c3148675597 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -1266,9 +1266,9 @@ static const struct l2c_init_data of_l2c310_data __initconst = { }; /* - * This is a variant of the of_l2c310_data with .sync set to - * NULL. Outer sync operations are not needed when the system is I/O - * coherent, and potentially harmful in certain situations (PCIe/PL310 + * This is a variant of the of_l2c310_data with .sync and .flush_range set to + * NULL. Outer sync and flush range operations are not needed when the system + * is I/O coherent, and potentially harmful in certain situations (PCIe/PL310 * deadlock on Armada 375/38x due to hardware I/O coherency). The * other operations are kept because they are infrequent (therefore do * not cause the deadlock in practice) and needed for secondary CPU @@ -1287,7 +1287,6 @@ static const struct l2c_init_data of_l2c310_coherent_data __initconst = { .outer_cache = { .inv_range = l2c210_inv_range, .clean_range = l2c210_clean_range, - .flush_range = l2c210_flush_range, .flush_all = l2c210_flush_all, .disable = l2c310_disable, .resume = l2c310_resume,