From patchwork Wed Aug 12 04:42:32 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 6995701 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E85DF9F7B4 for ; Wed, 12 Aug 2015 04:47:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0EE602070D for ; Wed, 12 Aug 2015 04:47:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23D7620534 for ; Wed, 12 Aug 2015 04:47:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZPNvJ-00089y-Uk; Wed, 12 Aug 2015 04:45:57 +0000 Received: from mail-ig0-f194.google.com ([209.85.213.194]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZPNv8-0007zh-Tm; Wed, 12 Aug 2015 04:45:49 +0000 Received: by igbjg10 with SMTP id jg10so767309igb.0; Tue, 11 Aug 2015 21:45:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=O+cYCfgTCIJSLmEKH2WwvT2YZK1IoAO0LKtsS72TmXE=; b=m8Dx/yZhCvQ30uOncp0mj4b9MCQBjg4Ra4qGjQwz4LqP4C3SZMvB7BzXbvwKGbmRt6 FiOE/507vEyf0MFR9mTZmJwgbJH9hXu8oLZw7vVXQFpdr5WFW88MAaPxXa3oUNhLY9fr QJT3AxDCXlXgTSWveRyrIG/wucwNf739gACNKSQ6z7/ToEht2TFoDAlqawk+viyaDWS+ i3YwH7wThae624wkL7B3HZW1UpjFIMx2V1++Y2cBXoiV1C3nD7w/i8yK9YPd+zmbrJH1 YepT81PQY628jvLerZfevtV0jmqewbhX9z64PfUW2MeMOWA4nr+EqVI5dXSxSTZFxFnR IwwA== X-Received: by 10.50.93.99 with SMTP id ct3mr22105782igb.83.1439354725756; Tue, 11 Aug 2015 21:45:25 -0700 (PDT) Received: from localhost.localdomain ([172.245.164.28]) by smtp.gmail.com with ESMTPSA id s12sm3134827ioe.14.2015.08.11.21.45.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 11 Aug 2015 21:45:24 -0700 (PDT) From: Caesar Wang To: ulf.hansson@linaro.org, khilman@linaro.org, heiko@sntech.de Subject: [PATCH v16 4/4] ARM: dts: add the support power-domain node on RK3288 SoCs Date: Wed, 12 Aug 2015 12:42:32 +0800 Message-Id: <1439354552-20098-5-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1439354552-20098-1-git-send-email-wxt@rock-chips.com> References: <1439354552-20098-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150811_214547_191564_3939B1AF X-CRM114-Status: GOOD ( 15.01 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, "jinkun.hong" , dmitry.torokhov@gmail.com, dianders@chromium.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, tomasz.figa@gmail.com, linux-arm-kernel@lists.infradead.org, wxt@rock-chips.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP We can add more domains node in the future. This patch add the needed clocks into power-controller. As the discuess about all the device clocks being listed in the power-domains itself. There are several reasons as follows: Firstly, the clocks need be turned off to save power when the system enter the suspend state. So we need to enumerate the clocks in the dts. In order to power domain can turn on and off. Secondly, the reset-circuit should reset be synchronous on RK3288, then sync revoked. So we need to enable clocks of all devices. In other words, we have to enable the clocks before you operate them if all the device clocks are included in someone domians. Someone wish was to get the clocks by reading the clocks from the device nodes, We can do that but we can solve the above issues. Anyway, the best ideas we can fix it in the future SoCs. Signed-off-by: jinkun.hong Signed-off-by: Caesar Wang --- Changes in v16: - Manually copy the problem in patch v15. - rebase the description. Series-changes: 15 - As Tomasz remarked previously the dts should represent the hardware and the power-domains are part of the pmu. Series-changes: 12 - Remove essential clocks from rk3288 PD_VIO domain, Some clocks are essential for the system health and should not be turned down. However there is no owner for them so if they listed as belonging to power domain we'll try toggling them up and down during power domain transition. As a result we either fail to suspend or resume the system. Series-changes: 10 - fix missing the #include . - remove the notes. Series-changes: 9 - add decription for power-doamin node. Series-changes: 8 - DTS go back to v2. Series-changes: 3 - Decomposition power-controller, changed to multiple controller (gpu-power-controller, hevc-power-controller). Series-changes: 2 - make pd_vio clocks all one entry per line and alphabetize. - power: power-controller move back to pinctrl: pinctrl. arch/arm/boot/dts/rk3288.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 22316d0..161931d 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -44,6 +44,7 @@ #include #include #include +#include #include "skeleton.dtsi" / { @@ -590,8 +591,65 @@ }; pmu: power-management@ff730000 { - compatible = "rockchip,rk3288-pmu", "syscon"; + compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; reg = <0xff730000 0x100>; + + power: power-controller { + compatible = "rockchip,rk3288-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu { + reg = ; + clocks = <&cru ACLK_GPU>; + }; + + pd_hevc { + reg = ; + clocks = <&cru ACLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, + <&cru SCLK_HEVC_CORE>, + <&cru HCLK_HEVC>; + }; + + pd_vio { + reg = ; + clocks = <&cru ACLK_IEP>, + <&cru ACLK_ISP>, + <&cru ACLK_RGA>, + <&cru ACLK_VIP>, + <&cru ACLK_VOP0>, + <&cru ACLK_VOP1>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru HCLK_IEP>, + <&cru HCLK_ISP>, + <&cru HCLK_RGA>, + <&cru HCLK_VIP>, + <&cru HCLK_VOP0>, + <&cru HCLK_VOP1>, + <&cru PCLK_EDP_CTRL>, + <&cru PCLK_HDMI_CTRL>, + <&cru PCLK_LVDS_PHY>, + <&cru PCLK_MIPI_CSI>, + <&cru PCLK_MIPI_DSI0>, + <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_EDP_24M>, + <&cru SCLK_EDP>, + <&cru SCLK_HDMI_CEC>, + <&cru SCLK_HDMI_HDCP>, + <&cru SCLK_ISP_JPE>, + <&cru SCLK_ISP>, + <&cru SCLK_RGA>; + }; + + pd_video { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + }; + }; }; sgrf: syscon@ff740000 {