From patchwork Wed Aug 12 08:24:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chaotian Jing X-Patchwork-Id: 6997951 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EFDB3C05AD for ; Wed, 12 Aug 2015 08:32:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2034120712 for ; Wed, 12 Aug 2015 08:32:49 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1CF482070D for ; Wed, 12 Aug 2015 08:32:48 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZPRR5-0001eH-Ur; Wed, 12 Aug 2015 08:30:59 +0000 Received: from [210.61.82.183] (helo=mailgw01.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZPRQt-0001VB-L5 for linux-arm-kernel@lists.infradead.org; Wed, 12 Aug 2015 08:30:48 +0000 X-Listener-Flag: 11101 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 439147763; Wed, 12 Aug 2015 16:24:36 +0800 Received: from mhfsdcap03.mhfswrd (10.17.3.153) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Wed, 12 Aug 2015 16:24:35 +0800 From: Chaotian Jing To: Rob Herring , Matthias Brugger , Chris Ball , Ulf Hansson Subject: [PATCH 3/4] arm64: dts: mediatek: Support SD/EMMC SDR104/HS200/HS400 Date: Wed, 12 Aug 2015 16:24:04 +0800 Message-ID: <1439367845-5891-4-git-send-email-chaotian.jing@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1439367845-5891-1-git-send-email-chaotian.jing@mediatek.com> References: <1439367845-5891-1-git-send-email-chaotian.jing@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150812_013048_107576_253AD68B X-CRM114-Status: GOOD ( 12.55 ) X-Spam-Score: -1.1 (-) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , James Liao , Catalin Marinas , Wenbin Mei , Will Deacon , Daniel Kurtz , Russell King - ARM Linux , Hongzhou Yang , Chaotian Jing , "Joe.C" , devicetree@vger.kernel.org, Arnd Bergmann , bin.zhang@mediatek.com, linux-gpio@vger.kernel.org, linux-mediatek@lists.infradead.org, Eddie Huang , linux-arm-kernel@lists.infradead.org, Liuquan Ji , srv_heupstream@mediatek.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Yong Mao , Sascha Hauer Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add 400Mhz source clock for EMMC HS400 mode Support EMMC DDR50/HS200/HS400 of mt8173-evb Support SD SDR25/SDR50/DDR50/SDR104 of mt8173-evb Signed-off-by: Chaotian Jing --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 10 ++++++++-- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 5 +++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 4be66ca..cd5317f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -70,8 +70,11 @@ pinctrl-0 = <&mmc0_pins_default>; pinctrl-1 = <&mmc0_pins_uhs>; bus-width = <8>; - max-frequency = <50000000>; + max-frequency = <200000000>; cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; vmmc-supply = <&mt6397_vemc_3v3_reg>; vqmmc-supply = <&mt6397_vio18_reg>; non-removable; @@ -83,9 +86,12 @@ pinctrl-0 = <&mmc1_pins_default>; pinctrl-1 = <&mmc1_pins_uhs>; bus-width = <4>; - max-frequency = <50000000>; + max-frequency = <200000000>; cap-sd-highspeed; sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; cd-gpios = <&pio 132 0>; vmmc-supply = <&mt6397_vmch_reg>; vqmmc-supply = <&mt6397_vmc_reg>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index d18ee42..495ed94 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -450,8 +450,9 @@ reg = <0 0x11230000 0 0x1000>; interrupts = ; clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&topckgen CLK_TOP_MSDC50_0_H_SEL>; - clock-names = "source", "hclk"; + <&topckgen CLK_TOP_MSDC50_0_H_SEL>, + <&topckgen CLK_TOP_MSDCPLL_D2>; + clock-names = "source", "hclk", "400Mhz_clk"; status = "disabled"; };