From patchwork Fri Aug 14 18:28:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 7019151 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9423CC05AD for ; Fri, 14 Aug 2015 18:31:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ABE6220614 for ; Fri, 14 Aug 2015 18:31:43 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9384420811 for ; Fri, 14 Aug 2015 18:31:42 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZQJj6-0002gG-AE; Fri, 14 Aug 2015 18:29:12 +0000 Received: from mail-wi0-x236.google.com ([2a00:1450:400c:c05::236]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZQJic-0002Nz-1g for linux-arm-kernel@lists.infradead.org; Fri, 14 Aug 2015 18:28:42 +0000 Received: by wibhh20 with SMTP id hh20so29652630wib.0 for ; Fri, 14 Aug 2015 11:28:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=2XqWgib5IZNBVHDTY+XJyQboBQCxMGZNoT75jODmLAE=; b=Sg4ONGlW6KGKin5AxHKofa14/LSWZQn0hL1QHVPTTOmkKTOUEEnxiietSnSbfoh7ro ezGojEB9z3fbT0wFqgrzW8nqKRLE9IxBfh1w4PuFfP0seI0N/RNgCM19RdPZz1sc1M+3 zulMKgxBYhtYc4O1SiuLleexdi9f0tSchAcuPWHNgmd33dXRnLaywRPYNLyzTPSyoOPE FaxI+lfsgCswCbw3boBxXdnyAuWXPGAERQGcZ78i4sbyRNk114mgtm2WZDwXburrbZ5Y yTGZw0dsbEz/gPonJR7vlzUeeEaBhKqa4uMvnSiY5Rt7oBu317RBLdnKEr+md8vhvoHq t+wg== X-Received: by 10.180.108.103 with SMTP id hj7mr9028474wib.11.1439576900467; Fri, 14 Aug 2015 11:28:20 -0700 (PDT) Received: from rric.localdomain (x5ce0c315.dyn.telefonica.de. [92.224.195.21]) by smtp.gmail.com with ESMTPSA id fn8sm4270672wib.2.2015.08.14.11.28.19 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 14 Aug 2015 11:28:20 -0700 (PDT) From: Robert Richter To: Marc Zygnier , Thomas Gleixner , Jason Cooper Subject: [PATCH v4 4/5] irqchip, gicv3-its: Add HW revision detection and configuration Date: Fri, 14 Aug 2015 20:28:04 +0200 Message-Id: <1439576885-15621-5-git-send-email-rric@kernel.org> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1439576885-15621-1-git-send-email-rric@kernel.org> References: <1439576885-15621-1-git-send-email-rric@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150814_112842_294079_41E28FA6 X-CRM114-Status: GOOD ( 16.00 ) X-Spam-Score: -2.4 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Robert Richter , Tirumalesh Chalamarla , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Robert Richter Some GIC revisions require an individual configuration to esp. add workarounds for HW bugs. This patch implements generic code to parse the hw revision provided by an IIDR register value and runs specific code if hw matches. There are functions that read the IIDR registers for GICV3 and ITS (GICD_IIDR/GITS_IIDR) and then go through a list of init functions to be called for specific versions. A MIDR register value may also be used, this is especially useful for hw detection from a guest. The patch is needed to implement workarounds for HW errata in Cavium's ThunderX GICV3. v4: * only enable hw detection for its in its_enable_quirks() * removed gicv3_check_capabilities() v3: * use arm64 errata framework for midr check v2: * adding MIDR check Signed-off-by: Robert Richter --- drivers/irqchip/irq-gic-common.c | 11 +++++++++++ drivers/irqchip/irq-gic-common.h | 9 +++++++++ drivers/irqchip/irq-gic-v3-its.c | 15 +++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index 9448e391cb71..ee789b07f2d1 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -21,6 +21,17 @@ #include "irq-gic-common.h" +void gic_check_capabilities(u32 iidr, const struct gic_capabilities *cap, + void *data) +{ + for (; cap->desc; cap++) { + if (cap->iidr != (cap->mask & iidr)) + continue; + cap->init(data); + pr_info("%s\n", cap->desc); + } +} + int gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)) { diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h index 35a9884778bd..ca12635bbe3c 100644 --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -20,10 +20,19 @@ #include #include +struct gic_capabilities { + const char *desc; + void (*init)(void *data); + u32 iidr; + u32 mask; +}; + int gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)); void gic_dist_config(void __iomem *base, int gic_irqs, void (*sync_access)(void)); void gic_cpu_config(void __iomem *base, void (*sync_access)(void)); +void gic_check_capabilities(u32 iidr, const struct gic_capabilities *cap, + void *data); #endif /* _IRQ_GIC_COMMON_H */ diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 06131db7a198..697421e834ee 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -36,6 +36,7 @@ #include #include +#include "irq-gic-common.h" #include "irqchip.h" #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 << 0) @@ -1390,6 +1391,18 @@ static int its_force_quiescent(void __iomem *base) } } +static const struct gic_capabilities its_errata[] = { + { + } +}; + +static void its_enable_quirks(struct its_node *its) +{ + u32 iidr = readl_relaxed(its->base + GITS_IIDR); + + gic_check_capabilities(iidr, its_errata, its); +} + static int its_probe(struct device_node *node, struct irq_domain *parent) { struct resource res; @@ -1448,6 +1461,8 @@ static int its_probe(struct device_node *node, struct irq_domain *parent) } its->cmd_write = its->cmd_base; + its_enable_quirks(its); + err = its_alloc_tables(its); if (err) goto out_free_cmd;