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Mon, 24 Aug 2015 17:05:44 +0900 (KST) From: Pankaj Dubey To: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/7] drivers: soc: add support for exynos SROM driver Date: Mon, 24 Aug 2015 13:32:24 +0530 Message-id: <1440403348-8974-4-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 2.4.5 In-reply-to: <1440403348-8974-1-git-send-email-pankaj.dubey@samsung.com> References: <1440403348-8974-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHLMWRmVeSWpSXmKPExsWyRsSkVjfywq1Qg1snBS3+P3rNavH6haFF /+PXzBabHl9jtbi8aw6bxYzz+5gsFm39wm7RsYzRgcNj06pONo/NS+o9+rasYvTYfm0es8fn TXIBrFFcNimpOZllqUX6dglcGbO2XGEuuGJT8bftJ2sD4wajLkZODgkBE4nFnRPYIGwxiQv3 1gPZXBxCAisYJWbsm8IIU3R53mQWiMQsRokvq/axQjitTBLduy4xg1SxCehKPHk/F8wWEciW uNJ4nxmkiFmggVFi2co7YDuEBTwkpm48zwJiswioSmyYuJwJxOYVcJeY+eIv0DoOoHVyEkub a0HCnEDl9yZPBZspBFTyfuMEsPMkBJaxSzSfegg1R0Di2+RDLBC9shKbDjBDXC0pcXDFDZYJ jMILGBlWMYqmFiQXFCelFxnpFSfmFpfmpesl5+duYgQG++l/z/p2MN48YH2IUYCDUYmHd4XZ rVAh1sSy4srcQ4ymQBsmMkuJJucDYyqvJN7Q2MzIwtTE1NjI3NJMSZw3QepnsJBAemJJanZq akFqUXxRaU5q8SFGJg5OqQbG6Mms3g4dN1VaxMy+nJd3f/x5yiT3mXNmM179dd/Zo5+ZS/LT kojbz6dmPc12TZTlNF2aHNAkkP7j2LJXhWv6v7JVWiXVBQXlzdjmLXV35sbDFrHZHzg+TDfZ veOvHg+jWnRnkqX3X4lyxhbxAyKq/77MvTnl7Jp01lsPU26Zlws+vBP1lmm/EktxRqKhFnNR cSIAHqUBkHECAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrNIsWRmVeSWpSXmKPExsVy+t9jQd3IC7dCDQ794rD4/+g1q8XrF4YW /Y9fM1tsenyN1eLyrjlsFjPO72OyWLT1C7tFxzJGBw6PTas62Tw2L6n36NuyitFj+7V5zB6f N8kFsEY1MNpkpCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXm AF2ipFCWmFMKFApILC5W0rfDNCE0xE3XAqYxQtc3JAiux8gADSSsYcyYteUKc8EVm4q/bT9Z Gxg3GHUxcnJICJhIXJ43mQXCFpO4cG89WxcjF4eQwCxGiS+r9rFCOK1MEt27LjGDVLEJ6Eo8 eT8XzBYRyJa40nifGaSIWaCBUWLZyjtsIAlhAQ+JqRvPg41lEVCV2DBxOROIzSvgLjHzxV/G LkYOoHVyEkuba0HCnEDl9yZPBZspBFTyfuMEtgmMvAsYGVYxSqQWJBcUJ6XnGuallusVJ+YW l+al6yXn525iBEfUM6kdjAd3uR9iFOBgVOLhZbC8FSrEmlhWXJl7iFGCg1lJhFfp5c1QId6U xMqq1KL8+KLSnNTiQ4ymQHdNZJYSTc4HRnteSbyhsYm5qbGppYmFiZmlkjiv7IbNoUIC6Ykl qdmpqQWpRTB9TBycUg2MUo+8+JLnXeCbpXJ30ZaDUVt5Ky49P7/q5LX7OlqGvxakOGxV+XU4 dltwxnthuZX1eW+qS9/5nb4QV29xUXwt7y/Jm91hjMUd3x882Xb059rICJ4Lq93FDv4p5Opp t49Qdbj2bBfbA1+7Nx+zJvCc/NTqE3Er1khB4+Xs0PqvZsXS11ZXzHF/q8RSnJFoqMVcVJwI AAe4a+K+AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150824_010607_017859_8A6F6F79 X-CRM114-Status: GOOD ( 22.39 ) X-Spam-Score: -8.1 (--------) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thomas.ab@samsung.com, Pankaj Dubey , k.kozlowski@samsung.com, kgene@kernel.org, heiko@sntech.de MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds Exynos SROM controller driver which will handle save restore of SROM registers during S2R. Signed-off-by: Pankaj Dubey --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/samsung/Kconfig | 13 ++++ drivers/soc/samsung/Makefile | 1 + drivers/soc/samsung/exynos-srom.c | 143 ++++++++++++++++++++++++++++++++++++++ drivers/soc/samsung/exynos-srom.h | 51 ++++++++++++++ 6 files changed, 210 insertions(+) create mode 100644 drivers/soc/samsung/Kconfig create mode 100644 drivers/soc/samsung/Makefile create mode 100644 drivers/soc/samsung/exynos-srom.c create mode 100644 drivers/soc/samsung/exynos-srom.h diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 96ddecb..69107c9 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/mediatek/Kconfig" source "drivers/soc/qcom/Kconfig" +source "drivers/soc/samsung/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/ti/Kconfig" source "drivers/soc/versatile/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 7dc7c0d..34c4398 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_QCOM) += qcom/ +obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_SOC_TI) += ti/ diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig new file mode 100644 index 0000000..ea4bc2a --- /dev/null +++ b/drivers/soc/samsung/Kconfig @@ -0,0 +1,13 @@ +# +# SAMSUNG SoC drivers +# +menu "Samsung SOC driver support" + +config SOC_SAMSUNG + bool + +config EXYNOS_SROM + bool + depends on ARM && ARCH_EXYNOS + +endmenu diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile new file mode 100644 index 0000000..9c554d5 --- /dev/null +++ b/drivers/soc/samsung/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o diff --git a/drivers/soc/samsung/exynos-srom.c b/drivers/soc/samsung/exynos-srom.c new file mode 100644 index 0000000..d7c4aa7 --- /dev/null +++ b/drivers/soc/samsung/exynos-srom.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - SROM Controller support + * Author: Pankaj Dubey + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include "exynos-srom.h" + +static void __iomem *exynos_srom_base; + +static const unsigned long exynos_srom_offsets[] = { + /* SROM side */ + EXYNOS_SROM_BW, + EXYNOS_SROM_BC0, + EXYNOS_SROM_BC1, + EXYNOS_SROM_BC2, + EXYNOS_SROM_BC3, +}; + +/** + * struct exynos_srom_reg_dump: register dump of SROM Controller registers. + * @offset: srom register offset from the controller base address. + * @value: the value of register under the offset. + */ +struct exynos_srom_reg_dump { + u32 offset; + u32 value; +}; + +static struct exynos_srom_reg_dump *exynos_srom_regs; + +static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump( + const unsigned long *rdump, + unsigned long nr_rdump) +{ + struct exynos_srom_reg_dump *rd; + unsigned int i; + + rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL); + if (!rd) + return NULL; + + for (i = 0; i < nr_rdump; ++i) + rd[i].offset = rdump[i]; + + return rd; +} + +static const struct of_device_id of_exynos_srom_ids[] = { + { + .compatible = "samsung,exynos-srom", + }, + {}, +}; + +static int exynos_srom_probe(struct platform_device *pdev) +{ + struct device_node *np; + struct device *dev = &pdev->dev; + + np = dev->of_node; + exynos_srom_base = of_iomap(np, 0); + + if (!exynos_srom_base) { + pr_err("iomap of exynos srom controller failed\n"); + return -ENOMEM; + } + + exynos_srom_regs = exynos_srom_alloc_reg_dump(exynos_srom_offsets, + sizeof(exynos_srom_offsets)); + + if (!exynos_srom_regs) { + iounmap(exynos_srom_regs); + return -ENOMEM; + } + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static void exynos_srom_save(void __iomem *base, + struct exynos_srom_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) + rd->value = readl(base + rd->offset); + +} + +static void exynos_srom_restore(void __iomem *base, + const struct exynos_srom_reg_dump *rd, + unsigned int num_regs) +{ + for (; num_regs > 0; --num_regs, ++rd) + writel(rd->value, base + rd->offset); + +} + +static int exynos_srom_suspend(struct device *dev) +{ + exynos_srom_save(exynos_srom_base, exynos_srom_regs, + ARRAY_SIZE(exynos_srom_offsets)); + + return 0; +} + +static int exynos_srom_resume(struct device *dev) +{ + exynos_srom_restore(exynos_srom_base, exynos_srom_regs, + ARRAY_SIZE(exynos_srom_offsets)); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(exynos_srom_pm_ops, exynos_srom_suspend, exynos_srom_resume); + +static struct platform_driver exynos_srom_driver = { + .probe = exynos_srom_probe, + .driver = { + .name = "exynos-srom", + .of_match_table = of_exynos_srom_ids, + .pm = &exynos_srom_pm_ops, + }, +}; + +static int __init exynos_srom_init(void) +{ + return platform_driver_register(&exynos_srom_driver); +} +device_initcall(exynos_srom_init); diff --git a/drivers/soc/samsung/exynos-srom.h b/drivers/soc/samsung/exynos-srom.h new file mode 100644 index 0000000..34660c6 --- /dev/null +++ b/drivers/soc/samsung/exynos-srom.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Exynos SROMC register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __EXYNOS_SROM_H +#define __EXYNOS_SROM_H __FILE__ + +#define EXYNOS_SROMREG(x) (x) + +#define EXYNOS_SROM_BW EXYNOS_SROMREG(0x0) +#define EXYNOS_SROM_BC0 EXYNOS_SROMREG(0x4) +#define EXYNOS_SROM_BC1 EXYNOS_SROMREG(0x8) +#define EXYNOS_SROM_BC2 EXYNOS_SROMREG(0xc) +#define EXYNOS_SROM_BC3 EXYNOS_SROMREG(0x10) +#define EXYNOS_SROM_BC4 EXYNOS_SROMREG(0x14) +#define EXYNOS_SROM_BC5 EXYNOS_SROMREG(0x18) + +/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */ + +#define EXYNOS_SROM_BW__DATAWIDTH__SHIFT 0 +#define EXYNOS_SROM_BW__ADDRMODE__SHIFT 1 +#define EXYNOS_SROM_BW__WAITENABLE__SHIFT 2 +#define EXYNOS_SROM_BW__BYTEENABLE__SHIFT 3 + +#define EXYNOS_SROM_BW__CS_MASK 0xf + +#define EXYNOS_SROM_BW__NCS0__SHIFT 0 +#define EXYNOS_SROM_BW__NCS1__SHIFT 4 +#define EXYNOS_SROM_BW__NCS2__SHIFT 8 +#define EXYNOS_SROM_BW__NCS3__SHIFT 12 +#define EXYNOS_SROM_BW__NCS4__SHIFT 16 +#define EXYNOS_SROM_BW__NCS5__SHIFT 20 + +/* applies to same to BCS0 - BCS3 */ + +#define EXYNOS_SROM_BCX__PMC__SHIFT 0 +#define EXYNOS_SROM_BCX__TACP__SHIFT 4 +#define EXYNOS_SROM_BCX__TCAH__SHIFT 8 +#define EXYNOS_SROM_BCX__TCOH__SHIFT 12 +#define EXYNOS_SROM_BCX__TACC__SHIFT 16 +#define EXYNOS_SROM_BCX__TCOS__SHIFT 24 +#define EXYNOS_SROM_BCX__TACS__SHIFT 28 + +#endif /* __EXYNOS_SROM_H */