| Message ID | 1440405608-3995-6-git-send-email-kernel@martin.sperl.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 08/24/2015 02:40 AM, kernel@martin.sperl.org wrote: > From: Martin Sperl <kernel@martin.sperl.org> Patch description? > diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt b/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt > +Required properties: > +- compatible: Should be "brcm,bcm2835-aux-spi". > +- reg: Should contain register location and length for the spi block > + as well as for the common aux block control Is that meant to imply that reg should contain a single value that covers both the common aux registers and the SPI device, or two separate values, one for the aux common registers and another for the SPI device? Neither of those options sound correct. I would expect only a single entry which covered solely the SPI registers. The common aux registers are owned by the other brcm,bcm2835-aux binding. > +Example: > + > +spi1@7e215080 { > + compatible = "brcm,bcm2835-aux-spi"; > + reg = <0x7e215080 0x40>; That seems to match what I'd expect, but doesn't correspond to the description above. > +/* the necessary syscon config referenced above*/ > +aux_enable: aux_enable@0x7e215004 { It's not a "syscon"... > +Note that it also requires the GPIOs to be set up with the > +correct ALT-functions. > + > +For spi1 the following pins need to be set as: > +* ALT4: 19, 20, 21 (MISO, MOSI, SCK) > + > +For spi2 the following pins need to be set as: > +* ALT4: 40, 41, 42 (MISO, MOSI, SCK) > + > +CS-GPIOS need to get set as output - typically: > +* spi1: 18, 17, 16 (CS0, CS1, CS2) > +* spi2: 43, 44, 45 (CS0, CS1, CS2) That's generally true of any HW block, and has nothing to do with the binding for the device. I would suggest removing that chunk of text.
diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt b/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt new file mode 100644 index 0000000..2a69a3b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/brcm,bcm2835-aux-spi.txt @@ -0,1 +1,61 @@ +Broadcom BCM2835 auxiliar SPI1/2 controller + +The BCM2835 contains two forms of SPI master controller, one known simply as +SPI0, and the other known as the "Universal SPI Master"; part of the +auxiliary block. This binding applies to the SPI1/2 controller. + +Required properties: +- compatible: Should be "brcm,bcm2835-aux-spi". +- reg: Should contain register location and length for the spi block + as well as for the common aux block control +- interrupts: Should contain shared interrupt of the aux block +- clocks: The clock feeding the SPI controller. +- cs-gpios: the cs-gpios (native cs is NOT supported) + see also spi-bus.txt +- bcrm,aux-enable: the bcrm,bcm2835-aux-enable config entry to handle + enabling/disabling of the spi1/spi2/uart1 HW block + second "argument" is the mask to apply to the + enable register + +Example: + +spi1@7e215080 { + compatible = "brcm,bcm2835-aux-spi"; + reg = <0x7e215080 0x40>; + interrupts = <1 29>; + clocks = <&clk_spi>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>; + bcrm,aux-enable = <&aux_enable 2>; +}; + +spi2@7e2150c0 { + compatible = "brcm,bcm2835-aux-spi"; + reg = <0x7e2150c0 0x40>; + interrupts = <1 29>; + clocks = <&clk_spi>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>; + bcrm,aux-enable = <&aux_enable 4>; +}; + +/* the necessary syscon config referenced above*/ +aux_enable: aux_enable@0x7e215004 { + compatible = "bcrm,bcm2835-aux"; + reg = <0x7e215004 0x04>; +}; + +Note that it also requires the GPIOs to be set up with the +correct ALT-functions. + +For spi1 the following pins need to be set as: +* ALT4: 19, 20, 21 (MISO, MOSI, SCK) + +For spi2 the following pins need to be set as: +* ALT4: 40, 41, 42 (MISO, MOSI, SCK) + +CS-GPIOS need to get set as output - typically: +* spi1: 18, 17, 16 (CS0, CS1, CS2) +* spi2: 43, 44, 45 (CS0, CS1, CS2) --