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[1/1] ARM: DT: STi: STiH418: Fix mmc0 clock configuration

Message ID 1440409204-11108-1-git-send-email-gabriel.fernandez@linaro.org (mailing list archive)
State New, archived
Headers show

Commit Message

Gabriel Fernandez Aug. 24, 2015, 9:40 a.m. UTC 
This patch configure correctly the MMC-0 clock for STiH418 platform.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
 arch/arm/boot/dts/stih418-b2199.dts | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Maxime Coquelin Aug. 24, 2015, 9:52 a.m. UTC | #1 
Hi Gabriel,

On 08/24/2015 11:40 AM, Gabriel Fernandez wrote:
> This patch configure correctly the MMC-0 clock for STiH418 platform.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
> ---
>   arch/arm/boot/dts/stih418-b2199.dts | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
> index 82eee39..7a03ca6 100644
> --- a/arch/arm/boot/dts/stih418-b2199.dts
> +++ b/arch/arm/boot/dts/stih418-b2199.dts
> @@ -85,6 +85,10 @@
>   			sd-uhs-sdr50;
>   			sd-uhs-sdr104;
>   			sd-uhs-ddr50;
> +
> +			assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
> +			assigned-clock-parents = <&clk_s_c0_pll1 0>;
> +			assigned-clock-rates = <200000000>;

Thanks for the fix, but I would rather define the parent and rate in the 
SoC dtsi file, i.e. stih418.dtsi.
If you agree to change, you can add:
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks!
Maxime
diff mbox

Patch

diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts
index 82eee39..7a03ca6 100644
--- a/arch/arm/boot/dts/stih418-b2199.dts
+++ b/arch/arm/boot/dts/stih418-b2199.dts
@@ -85,6 +85,10 @@ 
 			sd-uhs-sdr50;
 			sd-uhs-sdr104;
 			sd-uhs-ddr50;
+
+			assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
+			assigned-clock-parents = <&clk_s_c0_pll1 0>;
+			assigned-clock-rates = <200000000>;
 		};
 
 		miphy28lp_phy: miphy28lp@9b22000 {