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Tue, 25 Aug 2015 09:36:25 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by webmail.altera.com (66.35.236.227) with Microsoft SMTP Server (TLS) id 14.3.174.1; Tue, 25 Aug 2015 02:35:42 -0700 Received: from leyfoon-vm (pg-lftan-l.altera.com [137.57.103.123]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with SMTP id t7P9aIM3015431; Tue, 25 Aug 2015 02:36:19 -0700 (PDT) Received: by leyfoon-vm (sSMTP sendmail emulation); Tue, 25 Aug 2015 17:36:17 +0800 From: Ley Foon Tan To: Bjorn Helgaas , Russell King , Marc Zyngier Subject: [PATCH v5 4/5] Documentation: dt-bindings: pci: altera pcie device tree binding Date: Tue, 25 Aug 2015 17:35:47 +0800 Message-ID: <1440495348-2666-5-git-send-email-lftan@altera.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1440495348-2666-1-git-send-email-lftan@altera.com> References: <1440495348-2666-1-git-send-email-lftan@altera.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BN1BFFO11FD008; 1:h6RCg5VsnHrjJkvT9tOaXG4+aSjPIya7Pr+kC6A0mR76D39OsTOG6RFMzMIn47Q3n/lrF9rWPFDBNerCtfuEEQ2/LYKXxng7/cAGU8BM0ICcvDQvr8Ld5LswGJMAfJsDAErFRn1uwKx9dponJU7qnhrTvSnOxWV/F5D+vVcW+C1Ww/d+yQE2qHVsS9tCOrRs039yWBBLpo5X4O7n3L4uiSjwzagWDoDHxXeRHi0NbtJGRf2G0bURoxcbZbvO2/LM+9SdWizlucLf9aB9IBOy7xFBy40oIJZ2Np+fK6RSOlme4ogbkJ3l2JCWk0BpjkEfGZbqnHz9J1cgpUMDIkmAb6ST+QUCT7PonFnvgeoaWjdZ4XnUKLyrt3ON4Quz+XVr X-Forefront-Antispam-Report: CIP:66.35.236.227; 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Signed-off-by: Ley Foon Tan --- .../devicetree/bindings/pci/altera-pcie-msi.txt | 28 +++++++++++++ .../devicetree/bindings/pci/altera-pcie.txt | 49 ++++++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt new file mode 100644 index 0000000..53ad2388 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt @@ -0,0 +1,28 @@ +* Altera PCIe MSI controller + +Required properties: +- compatible: should contain "altr,msi-1.0" +- reg: specifies the physical base address of the controller and + the length of the memory mapped region. +- reg-names: must include the following entries: + "csr": CSR registers + "vector_slave": vectors slave port region +- interrupt-parent: interrupt source phandle. +- interrupts: specifies the interrupt source of the parent interrupt + controller. The format of the interrupt specifier depends on the + parent interrupt controller. +- num-vectors: number of vectors, range 1 to 32. +- msi-controller: indicates that this is MSI controller node + + +Example +msi0: msi@0xFF200000 { + compatible = "altr,msi-1.0"; + reg = <0xFF200000 0x00000010 + 0xFF200010 0x00000080>; + reg-names = "csr", "vector_slave"; + interrupt-parent = <&hps_0_arm_gic_0>; + interrupts = <0 42 4>; + msi-controller = <1>; + num-vectors = <32>; +}; diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt new file mode 100644 index 0000000..4440db1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt @@ -0,0 +1,49 @@ +* Altera PCIe controller + +Required properties: +- compatible : should contain "altr,pcie-root-port-1.0" +- reg: a list of physical base address and length for TXS and CRA. +- reg-names: must include the following entries: + "Txs" or "txs": TX slave port region + "Cra" or "cra": Control register access region +- interrupt-parent: interrupt source phandle. +- interrupts: specifies the interrupt source of the parent interrupt controller. + The format of the interrupt specifier depends on the parent interrupt + controller. +- device_type: must be "pci" +- #address-cells: set to <3> +- #size-cells: set to <2> +- #interrupt-cells: set to <1> +- ranges: describes the translation of addresses for root ports and standard + PCI regions. +- interrupt-map-mask and interrupt-map: standard PCI properties to define the + mapping of the PCIe interface to interrupt numbers. + +Optional properties: +- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe + controller. +- bus-range: PCI bus numbers covered + +Example + pcie_0: pcie@0xc00000000 { + compatible = "altr,pcie-root-port-1.0"; + reg = <0xc0000000 0x20000000>, + <0xff220000 0x00004000>; + reg-names = "Txs", "Cra"; + interrupt-parent = <&hps_0_arm_gic_0>; + interrupts = <0 40 4>; + interrupt-controller; + #interrupt-cells = <1>; + bus-range = <0x0 0xFF>; + device_type = "pci"; + msi-parent = <&msi_to_gic_gen_0>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_0 1>, + <0 0 0 2 &pcie_0 2>, + <0 0 0 3 &pcie_0 3>, + <0 0 0 4 &pcie_0 4>; + ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000 + 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>; + };